Date: Mon, 15 Jun 2015 18:54:26 GMT From: mihai@FreeBSD.org To: svn-soc-all@FreeBSD.org Subject: socsvn commit: r287126 - in soc2015/mihai/bhyve-on-arm-head/sys: arm/conf arm/fvp_ve-cortex_a15x1 arm/vexpress boot/fdt/dts/arm Message-ID: <201506151854.t5FIsQxh081916@socsvn.freebsd.org>
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Author: mihai Date: Mon Jun 15 18:54:25 2015 New Revision: 287126 URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=287126 Log: sys/arm: renaming vexpress into fvp_ve-cortex_a15x1 - the real name of the fast model platform Added: soc2015/mihai/bhyve-on-arm-head/sys/arm/conf/FVP_VE_CORTEX_A15x1 soc2015/mihai/bhyve-on-arm-head/sys/arm/fvp_ve-cortex_a15x1/ soc2015/mihai/bhyve-on-arm-head/sys/arm/fvp_ve-cortex_a15x1/files.fvp_ve-cortex_a15x1 soc2015/mihai/bhyve-on-arm-head/sys/arm/fvp_ve-cortex_a15x1/fvp_ve-cortex_a15x1_common.c soc2015/mihai/bhyve-on-arm-head/sys/arm/fvp_ve-cortex_a15x1/fvp_ve-cortex_a15x1_machdep.c soc2015/mihai/bhyve-on-arm-head/sys/arm/fvp_ve-cortex_a15x1/fvp_ve-cortex_a15x1_semihosting.S soc2015/mihai/bhyve-on-arm-head/sys/arm/fvp_ve-cortex_a15x1/fvp_ve-cortex_a15x1_semihosting.h soc2015/mihai/bhyve-on-arm-head/sys/arm/fvp_ve-cortex_a15x1/sp804.c soc2015/mihai/bhyve-on-arm-head/sys/boot/fdt/dts/arm/fvp_ve-cortex_a15x1.dts soc2015/mihai/bhyve-on-arm-head/sys/boot/fdt/dts/arm/fvp_ve-motherboard.dtsi Deleted: soc2015/mihai/bhyve-on-arm-head/sys/arm/conf/VEXPRESS soc2015/mihai/bhyve-on-arm-head/sys/arm/vexpress/ soc2015/mihai/bhyve-on-arm-head/sys/boot/fdt/dts/arm/rtsm_ve-cortex_a15x1.dts soc2015/mihai/bhyve-on-arm-head/sys/boot/fdt/dts/arm/rtsm_ve-motherboard.dtsi Added: soc2015/mihai/bhyve-on-arm-head/sys/arm/conf/FVP_VE_CORTEX_A15x1 ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ soc2015/mihai/bhyve-on-arm-head/sys/arm/conf/FVP_VE_CORTEX_A15x1 Mon Jun 15 18:54:25 2015 (r287126) @@ -0,0 +1,73 @@ +# +# FVP_VE_CORTEX_A15x1 - custom configuration +# + +ident ./FVP_VE_CORTEX_A15x1 + +makeoption ARM_LITTLE_ENDIAN + +cpu CPU_CORTEXA +machine arm armv6 +makeoptions CONF_CFLAGS="-march=armv7a" + +include "std.armv6" + +files "../fvp_ve-cortex_a15x1/files.fvp_ve-cortex_a15x1" + +options KERNVIRTADDR=0xc0200000 +makeoptions KERNVIRTADDR=0xc0200000 +options KERNPHYSADDR=0xc0200000 +makeoptions KERNPHYSADDR=0xc0200000 +options PHYSADDR=0xc0000000 + +options HZ=100 +options SCHED_ULE # ULE scheduler +#options PLATFORM +#options SMP # Enable multiple cores + +nooptions FREEBSD_BOOT_LOADER + +# Debugging for use in -current +makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols +options BREAK_TO_DEBUGGER +options DEBUG +options EARLY_PRINTF +options VERBOSE_SYSINIT # Enable verbose sysinit messages +options KDB # Enable kernel debugger support +# For minimum debugger support (stable branch) use: +options KDB_TRACE # Print a stack trace for a panic +# For full debugger support use this instead: +options DDB # Enable the kernel debugger +options INVARIANTS # Enable calls of extra sanity checking +options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS +#options WITNESS # Enable checks to detect deadlocks and cycles +#options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed +#options DIAGNOSTIC + +#options ROOTDEVNAME=\"ufs:/dev/da0\" + +# Pseudo devices + +device loop +device ether +device random +device pty +device md +device bpf + +# Serial ports +device uart +device pl011 + +# I2C +device iic +device iicbus + +# GPIO +device gpio + + +# Flattened Device Tree +options FDT # Configure using FDT/DTB data +options FDT_DTB_STATIC +makeoptions FDT_DTS_FILE=fvp_ve-cortex_a15x1.dts Added: soc2015/mihai/bhyve-on-arm-head/sys/arm/fvp_ve-cortex_a15x1/files.fvp_ve-cortex_a15x1 ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ soc2015/mihai/bhyve-on-arm-head/sys/arm/fvp_ve-cortex_a15x1/files.fvp_ve-cortex_a15x1 Mon Jun 15 18:54:25 2015 (r287126) @@ -0,0 +1,13 @@ +kern/kern_clocksource.c standard + +arm/arm/bus_space_base.c standard +arm/arm/bus_space_generic.c standard +arm/arm/bus_space_asm_generic.S standard +arm/arm/gic.c standard + +arm/fvp_ve-cortex_a15x1/sp804.c standard +arm/fvp_ve-cortex_a15x1/fvp_ve-cortex_a15x1_common.c standard +arm/fvp_ve-cortex_a15x1/fvp_ve-cortex_a15x1_machdep.c standard + +arm/fvp_ve-cortex_a15x1/fvp_ve-cortex_a15x1_semihosting.S standard + Added: soc2015/mihai/bhyve-on-arm-head/sys/arm/fvp_ve-cortex_a15x1/fvp_ve-cortex_a15x1_common.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ soc2015/mihai/bhyve-on-arm-head/sys/arm/fvp_ve-cortex_a15x1/fvp_ve-cortex_a15x1_common.c Mon Jun 15 18:54:25 2015 (r287126) @@ -0,0 +1,72 @@ +/*- + * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD. + * All rights reserved. + * + * Developed by Semihalf. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of MARVELL nor the names of contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD: head/sys/arm/versatile/versatile_common.c 281085 2015-04-04 21:34:26Z andrew $"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/kernel.h> +#include <sys/malloc.h> +#include <sys/kdb.h> +#include <sys/reboot.h> + +#include <dev/fdt/fdt_common.h> +#include <dev/ofw/openfirm.h> + +#include <machine/bus.h> +#include <machine/vmparam.h> + +struct fdt_fixup_entry fdt_fixup_table[] = { + { NULL, NULL } +}; + +static int +fdt_intc_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, + int *pol) +{ + + if (!fdt_is_compatible(node, "arm,cortex-a15-gic")) + return (ENXIO); + + *interrupt = fdt32_to_cpu(intr[0]); + *trig = INTR_TRIGGER_CONFORM; + *pol = INTR_POLARITY_CONFORM; + + return (0); +} + + +fdt_pic_decode_t fdt_pic_table[] = { + &fdt_intc_decode_ic, + NULL +}; Added: soc2015/mihai/bhyve-on-arm-head/sys/arm/fvp_ve-cortex_a15x1/fvp_ve-cortex_a15x1_machdep.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ soc2015/mihai/bhyve-on-arm-head/sys/arm/fvp_ve-cortex_a15x1/fvp_ve-cortex_a15x1_machdep.c Mon Jun 15 18:54:25 2015 (r287126) @@ -0,0 +1,133 @@ +/*- + * Copyright (c) 2012 Oleksandr Tymoshenko. + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#include "opt_ddb.h" +#include "opt_platform.h" + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD: head/sys/arm/versatile/versatile_machdep.c 274668 2014-11-18 17:06:56Z imp $"); + +#define _ARM32_BUS_DMA_PRIVATE +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> + +#include <vm/vm.h> +#include <vm/pmap.h> + +#include <machine/bus.h> +#include <machine/devmap.h> +#include <machine/machdep.h> +#include <machine/platform.h> + +#include <dev/fdt/fdt_common.h> + +#include "fvp_ve-cortex_a15x1_semihosting.h" + +vm_offset_t +platform_lastaddr(void) +{ + + return (arm_devmap_lastaddr()); +} + +void +platform_probe_and_attach(void) +{ + +} + +void +platform_gpio_init(void) +{ + +} + +void +platform_late_init(void) +{ + +} + +int +platform_devmap_init(void) +{ + /* UART0 (PL011) */ + arm_devmap_add_entry(0x1c090000, 0x1000); + + /* Peripherals (CS3) */ +// arm_devmap_add_entry(0x1C000000, 0x4000000); + + return (0); +} + + + +struct arm32_dma_range * +bus_dma_get_range(void) +{ + + return (NULL); +} + +int +bus_dma_get_range_nb(void) +{ + + return (0); +} + +#ifdef EARLY_PRINTF + +static void +eputc(int c) +{ + char str[2]; + str[0] = c; + str[1] = 0; + + __semi_call(SYS_WRITE0, str); +} + +early_putc_t * early_putc = eputc; +#endif + +void +cpu_reset() +{ + printf("cpu_reset\n"); + while (1); +} + Added: soc2015/mihai/bhyve-on-arm-head/sys/arm/fvp_ve-cortex_a15x1/fvp_ve-cortex_a15x1_semihosting.S ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ soc2015/mihai/bhyve-on-arm-head/sys/arm/fvp_ve-cortex_a15x1/fvp_ve-cortex_a15x1_semihosting.S Mon Jun 15 18:54:25 2015 (r287126) @@ -0,0 +1,8 @@ + @ + @ Function for C code to make semihosting calls: + @ + .globl __semi_call +__semi_call: + svc 0x123456 + mov pc, lr + Added: soc2015/mihai/bhyve-on-arm-head/sys/arm/fvp_ve-cortex_a15x1/fvp_ve-cortex_a15x1_semihosting.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ soc2015/mihai/bhyve-on-arm-head/sys/arm/fvp_ve-cortex_a15x1/fvp_ve-cortex_a15x1_semihosting.h Mon Jun 15 18:54:25 2015 (r287126) @@ -0,0 +1,9 @@ +#ifndef SEMIHOSTING_H +#define SEMIHOSTING_H + +#define SYS_WRITE0 4 +#define SEMIHOSTING_SVC 0x123456 /* SVC comment field for semihosting */ + +int __semi_call(int id, ...); + +#endif /* ! SEMIHOSTING_H */ Added: soc2015/mihai/bhyve-on-arm-head/sys/arm/fvp_ve-cortex_a15x1/sp804.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ soc2015/mihai/bhyve-on-arm-head/sys/arm/fvp_ve-cortex_a15x1/sp804.c Mon Jun 15 18:54:25 2015 (r287126) @@ -0,0 +1,361 @@ +/* + * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> + * Copyright (c) 2012 Damjan Marion <dmarion@freebsd.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD: soc2015/mihai/bhyve-on-arm-head/sys/arm/versatile/sp804.c 283652 2015-04-04 21:34:26Z andrew $"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <sys/malloc.h> +#include <sys/rman.h> +#include <sys/timeet.h> +#include <sys/timetc.h> +#include <sys/watchdog.h> +#include <machine/bus.h> +#include <machine/cpu.h> +#include <machine/intr.h> + +#include <dev/fdt/fdt_common.h> +#include <dev/ofw/openfirm.h> +#include <dev/ofw/ofw_bus.h> +#include <dev/ofw/ofw_bus_subr.h> + +#include <machine/bus.h> + +#define SP804_TIMER1_LOAD 0x00 +#define SP804_TIMER1_VALUE 0x04 +#define SP804_TIMER1_CONTROL 0x08 +#define TIMER_CONTROL_EN (1 << 7) +#define TIMER_CONTROL_FREERUN (0 << 6) +#define TIMER_CONTROL_PERIODIC (1 << 6) +#define TIMER_CONTROL_INTREN (1 << 5) +#define TIMER_CONTROL_DIV1 (0 << 2) +#define TIMER_CONTROL_DIV16 (1 << 2) +#define TIMER_CONTROL_DIV256 (2 << 2) +#define TIMER_CONTROL_32BIT (1 << 1) +#define TIMER_CONTROL_ONESHOT (1 << 0) +#define SP804_TIMER1_INTCLR 0x0C +#define SP804_TIMER1_RIS 0x10 +#define SP804_TIMER1_MIS 0x14 +#define SP804_TIMER1_BGLOAD 0x18 +#define SP804_TIMER2_LOAD 0x20 +#define SP804_TIMER2_VALUE 0x24 +#define SP804_TIMER2_CONTROL 0x28 +#define SP804_TIMER2_INTCLR 0x2C +#define SP804_TIMER2_RIS 0x30 +#define SP804_TIMER2_MIS 0x34 +#define SP804_TIMER2_BGLOAD 0x38 + +#define SP804_PERIPH_ID0 0xFE0 +#define SP804_PERIPH_ID1 0xFE4 +#define SP804_PERIPH_ID2 0xFE8 +#define SP804_PERIPH_ID3 0xFEC +#define SP804_PRIMECELL_ID0 0xFF0 +#define SP804_PRIMECELL_ID1 0xFF4 +#define SP804_PRIMECELL_ID2 0xFF8 +#define SP804_PRIMECELL_ID3 0xFFC + +#define DEFAULT_FREQUENCY 1000000 +/* + * QEMU seems to have problem with full frequency + */ +#define DEFAULT_DIVISOR 16 +#define DEFAULT_CONTROL_DIV TIMER_CONTROL_DIV16 + +struct sp804_timer_softc { + struct resource* mem_res; + struct resource* irq_res; + void* intr_hl; + uint32_t sysclk_freq; + bus_space_tag_t bst; + bus_space_handle_t bsh; + struct timecounter tc; + bool et_enabled; + struct eventtimer et; + int timer_initialized; +}; + +/* Read/Write macros for Timer used as timecounter */ +#define sp804_timer_tc_read_4(reg) \ + bus_space_read_4(sc->bst, sc->bsh, reg) + +#define sp804_timer_tc_write_4(reg, val) \ + bus_space_write_4(sc->bst, sc->bsh, reg, val) + +static unsigned sp804_timer_tc_get_timecount(struct timecounter *); + +static unsigned +sp804_timer_tc_get_timecount(struct timecounter *tc) +{ + struct sp804_timer_softc *sc = tc->tc_priv; + return 0xffffffff - sp804_timer_tc_read_4(SP804_TIMER1_VALUE); +} + +static int +sp804_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) +{ + struct sp804_timer_softc *sc = et->et_priv; + uint32_t count, reg; + + if (first != 0) { + sc->et_enabled = 1; + + count = ((uint32_t)et->et_frequency * first) >> 32; + + sp804_timer_tc_write_4(SP804_TIMER2_LOAD, count); + reg = TIMER_CONTROL_32BIT | TIMER_CONTROL_INTREN | + TIMER_CONTROL_PERIODIC | DEFAULT_CONTROL_DIV | + TIMER_CONTROL_EN; + sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, reg); + + return (0); + } + + if (period != 0) { + panic("period"); + } + + return (EINVAL); +} + +static int +sp804_timer_stop(struct eventtimer *et) +{ + struct sp804_timer_softc *sc = et->et_priv; + uint32_t reg; + + sc->et_enabled = 0; + reg = sp804_timer_tc_read_4(SP804_TIMER2_CONTROL); + reg &= ~(TIMER_CONTROL_EN); + sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, reg); + + return (0); +} + +static int +sp804_timer_intr(void *arg) +{ + struct sp804_timer_softc *sc = arg; + static uint32_t prev = 0; + uint32_t x = 0; + + x = sp804_timer_tc_read_4(SP804_TIMER1_VALUE); + + prev =x ; + sp804_timer_tc_write_4(SP804_TIMER2_INTCLR, 1); + if (sc->et_enabled) { + if (sc->et.et_active) { + sc->et.et_event_cb(&sc->et, sc->et.et_arg); + } + } + + return (FILTER_HANDLED); +} + +static int +sp804_timer_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_is_compatible(dev, "arm,sp804")) { + device_set_desc(dev, "SP804 System Timer"); + return (BUS_PROBE_DEFAULT); + } + + return (ENXIO); +} + +static int +sp804_timer_attach(device_t dev) +{ + struct sp804_timer_softc *sc = device_get_softc(dev); + int rid = 0; + int i; + uint32_t id, reg; + phandle_t node; + pcell_t clock; + + sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); + if (sc->mem_res == NULL) { + device_printf(dev, "could not allocate memory resource\n"); + return (ENXIO); + } + + sc->bst = rman_get_bustag(sc->mem_res); + sc->bsh = rman_get_bushandle(sc->mem_res); + + /* Request the IRQ resources */ + sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); + if (sc->irq_res == NULL) { + device_printf(dev, "Error: could not allocate irq resources\n"); + return (ENXIO); + } + + sc->sysclk_freq = DEFAULT_FREQUENCY; + /* Get the base clock frequency */ + node = ofw_bus_get_node(dev); + if ((OF_getprop(node, "clock-frequency", &clock, sizeof(clock))) > 0) { + sc->sysclk_freq = fdt32_to_cpu(clock); + } + + /* Setup and enable the timer */ + if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_CLK, + sp804_timer_intr, NULL, sc, + &sc->intr_hl) != 0) { + bus_release_resource(dev, SYS_RES_IRQ, rid, + sc->irq_res); + device_printf(dev, "Unable to setup the clock irq handler.\n"); + return (ENXIO); + } + + sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, 0); + sp804_timer_tc_write_4(SP804_TIMER2_CONTROL, 0); + + /* + * Timer 1, timecounter + */ + sc->tc.tc_frequency = sc->sysclk_freq; + sc->tc.tc_name = "SP804 Time Counter"; + sc->tc.tc_get_timecount = sp804_timer_tc_get_timecount; + sc->tc.tc_poll_pps = NULL; + sc->tc.tc_counter_mask = ~0u; + sc->tc.tc_quality = 1000; + sc->tc.tc_priv = sc; + + sp804_timer_tc_write_4(SP804_TIMER1_VALUE, 0xffffffff); + sp804_timer_tc_write_4(SP804_TIMER1_LOAD, 0xffffffff); + reg = TIMER_CONTROL_PERIODIC | TIMER_CONTROL_32BIT; + sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, reg); + reg |= TIMER_CONTROL_EN; + sp804_timer_tc_write_4(SP804_TIMER1_CONTROL, reg); + tc_init(&sc->tc); + + /* + * Timer 2, event timer + */ + sc->et_enabled = 0; + sc->et.et_name = malloc(64, M_DEVBUF, M_NOWAIT | M_ZERO); + sprintf(sc->et.et_name, "SP804 Event Timer %d", + device_get_unit(dev)); + sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; + sc->et.et_quality = 1000; + sc->et.et_frequency = sc->sysclk_freq / DEFAULT_DIVISOR; + sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency; + sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; + sc->et.et_start = sp804_timer_start; + sc->et.et_stop = sp804_timer_stop; + sc->et.et_priv = sc; + et_register(&sc->et); + + id = 0; + for (i = 3; i >= 0; i--) { + id = (id << 8) | + (sp804_timer_tc_read_4(SP804_PERIPH_ID0 + i*4) & 0xff); + } + + device_printf(dev, "peripheral ID: %08x\n", id); + + id = 0; + for (i = 3; i >= 0; i--) { + id = (id << 8) | + (sp804_timer_tc_read_4(SP804_PRIMECELL_ID0 + i*4) & 0xff); + } + + device_printf(dev, "PrimeCell ID: %08x\n", id); + + sc->timer_initialized = 1; + + return (0); +} + +static device_method_t sp804_timer_methods[] = { + DEVMETHOD(device_probe, sp804_timer_probe), + DEVMETHOD(device_attach, sp804_timer_attach), + { 0, 0 } +}; + +static driver_t sp804_timer_driver = { + "timer", + sp804_timer_methods, + sizeof(struct sp804_timer_softc), +}; + +static devclass_t sp804_timer_devclass; + +DRIVER_MODULE(sp804_timer, simplebus, sp804_timer_driver, sp804_timer_devclass, 0, 0); + +void +DELAY(int usec) +{ + int32_t counts; + uint32_t first, last; + device_t timer_dev; + struct sp804_timer_softc *sc; + int timer_initialized = 0; + + timer_dev = devclass_get_device(sp804_timer_devclass, 0); + + if (timer_dev) { + sc = device_get_softc(timer_dev); + + if (sc) + timer_initialized = sc->timer_initialized; + } + + if (!timer_initialized) { + /* + * Timer is not initialized yet + */ + for (; usec > 0; usec--) + for (counts = 200; counts > 0; counts--) + /* Prevent gcc from optimizing out the loop */ + cpufunc_nullop(); + return; + } + + /* Get the number of times to count */ + counts = usec * ((sc->tc.tc_frequency / 1000000) + 1); + + first = sp804_timer_tc_get_timecount(&sc->tc); + + while (counts > 0) { + last = sp804_timer_tc_get_timecount(&sc->tc); + if (last == first) + continue; + if (last>first) { + counts -= (int32_t)(last - first); + } else { + counts -= (int32_t)((0xFFFFFFFF - first) + last); + } + first = last; + } +} Added: soc2015/mihai/bhyve-on-arm-head/sys/boot/fdt/dts/arm/fvp_ve-cortex_a15x1.dts ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ soc2015/mihai/bhyve-on-arm-head/sys/boot/fdt/dts/arm/fvp_ve-cortex_a15x1.dts Mon Jun 15 18:54:25 2015 (r287126) @@ -0,0 +1,127 @@ +/* + * ARM Ltd. Fast Models + * + * Versatile Express (VE) system model + * ARMCortexA15x1CT + * + * RTSM_VE_Cortex_A15x1.lisa + */ + +/dts-v1/; + +/ { + model = "RTSM_VE_Cortex_A15x1"; + compatible = "arm,rtsm_ve,cortex_a15x1", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x40000000>; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x2c001000 0 0x1000>, + <0 0x2c002000 0 0x2000>, + <0 0x2c004000 0 0x2000>, + <0 0x2c006000 0 0x2000>; + interrupts = <1 9 0xf04>; + }; + + timer { + compatible = "arm,armv7-timer"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <1>; + #size-cells = <1>; + ranges = /*<0 0 0x08000000 0x04000000>, + <1 0 0x14000000 0x04000000>, + <2 0 0x18000000 0x04000000>,*/ + <0 0 0x1c000000 0x04000000>; +/* <4 0 0x0c000000 0x04000000>, + <5 0 0x10000000 0x04000000>;*/ + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + + /include/ "rtsm_ve-motherboard.dtsi" + }; +}; + Added: soc2015/mihai/bhyve-on-arm-head/sys/boot/fdt/dts/arm/fvp_ve-motherboard.dtsi ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ soc2015/mihai/bhyve-on-arm-head/sys/boot/fdt/dts/arm/fvp_ve-motherboard.dtsi Mon Jun 15 18:54:25 2015 (r287126) @@ -0,0 +1,240 @@ +/* + * ARM Ltd. Fast Models + * + * Versatile Express (VE) system model + * Motherboard component + * + * VEMotherBoard.lisa + */ + + motherboard { + arm,v2m-memory-map = "rs1"; + compatible = "arm,rtsm_ve,vemotherboard", "simple-bus"; + #address-cells = <1>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + flash@0,00000000 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <4 0x00000000 0x04000000>; + bank-width = <4>; + }; + + vram@2,00000000 { + compatible = "arm,vexpress-vram"; + reg = <2 0x00000000 0x00800000>; + }; + + ethernet@2,02000000 { + compatible = "smsc,lan91c111"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; + }; + + iofpga@3,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x200000>; + + v2m_sysreg: sysreg@010000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_sysctl: sysctl@020000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + }; + + aaci@040000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x040000 0x1000>; + interrupts = <11>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; + + mmci@050000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x050000 0x1000>; + interrupts = <9 10>; + cd-gpios = <&v2m_sysreg 0 0>; + wp-gpios = <&v2m_sysreg 1 0>; + max-frequency = <12000000>; + vmmc-supply = <&v2m_fixed_3v3>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "mclk", "apb_pclk"; + }; + + kmi@060000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x060000 0x1000>; + interrupts = <12>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@070000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x070000 0x1000>; + interrupts = <13>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + v2m_serial0: uart@090000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: uart@0a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: uart@0b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: uart@0c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + wdt@0f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x1000>; + interrupts = <0>; + clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; + clock-names = "wdogclk", "apb_pclk"; + }; + + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + virtio_block@130000 { + compatible = "virtio,mmio"; + reg = <0x130000 0x200>; + interrupts = <42>; + }; + + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x1000>; + interrupts = <4>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; + + clcd@1f0000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f0000 0x1000>; + interrupts = <14>; + clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; + clock-names = "clcdclk", "apb_pclk"; + }; + }; + + v2m_fixed_3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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