Date: Tue, 04 Jan 2005 17:12:19 -0700 From: Phil Spuhler <phil@ridgetop-group.com> To: doc@FreeBSD.org Subject: UART frequency drift Message-ID: <41DB30E3.4090101@ridgetop-group.com>
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Hi, I have a question regarding your documentation on the UART. It says that the frequency drift on the asynchronous clocks can be up to 10% total. Shouldn't this be 5%? My reasoning on this is that if the bits are sampled in the center, the total frequency offset can be high enough to shift the sampling to the edge of the bit in 10 samples --> 50% shift / 10 samples = 5%. Cheers, -Phil
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