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Date:      Wed, 25 Aug 2010 11:49:48 +0000 (UTC)
From:      "Jayachandran C." <jchandra@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r211811 - head/sys/mips/rmi
Message-ID:  <201008251149.o7PBnmQv010456@svn.freebsd.org>

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Author: jchandra
Date: Wed Aug 25 11:49:48 2010
New Revision: 211811
URL: http://svn.freebsd.org/changeset/base/211811

Log:
  XLR PIC code update and style(9) fixes.
  
  - style(9) fixes to mips/rmi platform files
  - update pic.h to add pic_setup_intr() and use pic_setup_intr() for setting
    up interrupts which are routed thru PIC.
  - remove rmi_spin_mutex_safe and haslock, and make sure that the functions
    are called only after mutexes are available.

Modified:
  head/sys/mips/rmi/fmn.c
  head/sys/mips/rmi/intr_machdep.c
  head/sys/mips/rmi/iodi.c
  head/sys/mips/rmi/msgring.h
  head/sys/mips/rmi/pic.h
  head/sys/mips/rmi/xlr_machdep.c
  head/sys/mips/rmi/xlr_pci.c

Modified: head/sys/mips/rmi/fmn.c
==============================================================================
--- head/sys/mips/rmi/fmn.c	Wed Aug 25 11:11:14 2010	(r211810)
+++ head/sys/mips/rmi/fmn.c	Wed Aug 25 11:49:48 2010	(r211811)
@@ -362,14 +362,10 @@ register_msgring_handler(int major,
 	if (major >= MAX_TX_STNS)
 		return 1;
 
-	//dbg_msg("major=%d, action=%p, dev_id=%p\n", major, action, dev_id);
-
-	if (rmi_spin_mutex_safe)
-	  mtx_lock_spin(&msgrng_lock);
+	mtx_lock_spin(&msgrng_lock);
 	tx_stn_handlers[major].action = action;
 	tx_stn_handlers[major].dev_id = dev_id;
-	if (rmi_spin_mutex_safe)
-	  mtx_unlock_spin(&msgrng_lock);
+	mtx_unlock_spin(&msgrng_lock);
 
 	if (xlr_test_and_set(&msgring_int_enabled)) {
 		create_msgring_thread(0, 0);

Modified: head/sys/mips/rmi/intr_machdep.c
==============================================================================
--- head/sys/mips/rmi/intr_machdep.c	Wed Aug 25 11:11:14 2010	(r211810)
+++ head/sys/mips/rmi/intr_machdep.c	Wed Aug 25 11:49:48 2010	(r211811)
@@ -168,7 +168,7 @@ cpu_intr(struct trapframe *tf)
 			mips_intrcnt_inc(mips_intr_counters[i]);
 		}
 		write_c0_eirr64(1ULL << i);
-		pic_ack(i, 0);
+		pic_ack(i);
 		if (!ie || TAILQ_EMPTY(&ie->ie_handlers)) {
 			printf("stray interrupt %d\n", i);
 			continue;
@@ -176,7 +176,7 @@ cpu_intr(struct trapframe *tf)
 		if (intr_event_handle(ie, tf) != 0) {
 			printf("stray interrupt %d\n", i);
 		}
-		pic_delayed_ack(i, 0);
+		pic_delayed_ack(i);
 	}
 	critical_exit();
 }

Modified: head/sys/mips/rmi/iodi.c
==============================================================================
--- head/sys/mips/rmi/iodi.c	Wed Aug 25 11:11:14 2010	(r211810)
+++ head/sys/mips/rmi/iodi.c	Wed Aug 25 11:49:48 2010	(r211811)
@@ -91,53 +91,28 @@ struct iodi_softc *iodi_softc;	/* There 
 
 static int
 iodi_setup_intr(device_t dev, device_t child,
-    struct resource *ires, int flags, driver_filter_t * filt, driver_intr_t * intr, void *arg,
-    void **cookiep)
+    struct resource *ires, int flags, driver_filter_t * filt,
+    driver_intr_t *intr, void *arg, void **cookiep)
 {
-	int level;
-	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
-	xlr_reg_t reg;
 
-	/* FIXME is this the right place to fiddle with PIC? */
 	if (strcmp(device_get_name(child), "uart") == 0) {
 		/* FIXME uart 1? */
-		if (rmi_spin_mutex_safe)
-			mtx_lock_spin(&xlr_pic_lock);
-		level = PIC_IRQ_IS_EDGE_TRIGGERED(PIC_IRT_UART_0_INDEX);
-		xlr_write_reg(mmio, PIC_IRT_0_UART_0, 0x01);
-		xlr_write_reg(mmio, PIC_IRT_1_UART_0, ((1 << 31) | (level << 30) | (1 << 6) | (PIC_UART_0_IRQ)));
-		if (rmi_spin_mutex_safe)
-			mtx_unlock_spin(&xlr_pic_lock);
-		cpu_establish_hardintr("uart", filt,
-		    (driver_intr_t *) intr, (void *)arg, PIC_UART_0_IRQ, flags, cookiep);
-
+		cpu_establish_hardintr("uart", filt, intr, arg,
+		    PIC_UART_0_IRQ, flags, cookiep);
+		pic_setup_intr(PIC_IRT_UART_0_INDEX, PIC_UART_0_IRQ, 0x1);
 	} else if (strcmp(device_get_name(child), "rge") == 0) {
 		int irq;
 
 		/* This is a hack to pass in the irq */
 		irq = (intptr_t)ires->__r_i;
-		if (rmi_spin_mutex_safe)
-			mtx_lock_spin(&xlr_pic_lock);
-		reg = xlr_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
-		xlr_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE, reg | (1 << 6) | (1 << 30) | (1 << 31));
-		if (rmi_spin_mutex_safe)
-			mtx_unlock_spin(&xlr_pic_lock);
-		cpu_establish_hardintr("rge", filt, (driver_intr_t *) intr, (void *)arg, irq, flags, cookiep);
-
+		cpu_establish_hardintr("rge", filt, intr, arg, irq, flags,
+		    cookiep);
+		pic_setup_intr(irq - PIC_IRQ_BASE, irq, 0x1);
 	} else if (strcmp(device_get_name(child), "ehci") == 0) {
-		if (rmi_spin_mutex_safe)
-			mtx_lock_spin(&xlr_pic_lock);
-		reg = xlr_read_reg(mmio, PIC_IRT_1_BASE + PIC_USB_IRQ - PIC_IRQ_BASE);
-		xlr_write_reg(mmio, PIC_IRT_1_BASE + PIC_USB_IRQ - PIC_IRQ_BASE, reg | (1 << 6) | (1 << 30) | (1 << 31));
-		if (rmi_spin_mutex_safe)
-			mtx_unlock_spin(&xlr_pic_lock);
-		cpu_establish_hardintr("ehci", filt, (driver_intr_t *) intr, (void *)arg, PIC_USB_IRQ, flags, cookiep);
+		cpu_establish_hardintr("ehci", filt, intr, arg, PIC_USB_IRQ, flags,
+		    cookiep);
+		pic_setup_intr(PIC_USB_IRQ - PIC_IRQ_BASE, PIC_USB_IRQ, 0x1);
 	}
-	/*
-	 * This causes a panic and looks recursive to me (RRS).
-	 * BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt,
-	 * intr, arg, cookiep);
-	 */
 
 	return (0);
 }

Modified: head/sys/mips/rmi/msgring.h
==============================================================================
--- head/sys/mips/rmi/msgring.h	Wed Aug 25 11:11:14 2010	(r211810)
+++ head/sys/mips/rmi/msgring.h	Wed Aug 25 11:49:48 2010	(r211811)
@@ -25,6 +25,7 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ * $FreeBSD$
  *
  * RMI_BSD */
 #ifndef _RMI_MSGRING_H_
@@ -471,13 +472,13 @@ extern struct stn_cc xls_cc_table_sec;
 
 
 #define msgrng_access_save(lock, mflags) do {                \
-  if (rmi_spin_mutex_safe) mtx_lock_spin(lock);              \
+  mtx_lock_spin(lock);                                       \
   msgrng_flags_save(mflags);                                 \
  }while(0)
 
 #define msgrng_access_restore(lock, mflags) do {             \
   msgrng_flags_restore(mflags);                              \
-  if (rmi_spin_mutex_safe) mtx_unlock_spin(lock);            \
+  mtx_unlock_spin(lock);                                     \
  }while(0)
 
 #define msgrng_access_enable(mflags) do {   \

Modified: head/sys/mips/rmi/pic.h
==============================================================================
--- head/sys/mips/rmi/pic.h	Wed Aug 25 11:11:14 2010	(r211810)
+++ head/sys/mips/rmi/pic.h	Wed Aug 25 11:49:48 2010	(r211811)
@@ -32,219 +32,154 @@
 #define _RMI_PIC_H_
 #include <sys/cdefs.h>
 
-
-
-
-extern int rmi_spin_mutex_safe;
-
 #include <sys/lock.h>
 #include <sys/mutex.h>
 #include <mips/rmi/iomap.h>
 
-#define PIC_IRT_WD_INDEX     0
-#define PIC_IRT_TIMER_0_INDEX      1
-#define PIC_IRT_TIMER_1_INDEX      2
-#define PIC_IRT_TIMER_2_INDEX      3
-#define PIC_IRT_TIMER_3_INDEX      4
-#define PIC_IRT_TIMER_4_INDEX      5
-#define PIC_IRT_TIMER_5_INDEX      6
-#define PIC_IRT_TIMER_6_INDEX      7
-#define PIC_IRT_TIMER_7_INDEX      8
-#define PIC_IRT_CLOCK_INDEX        PIC_IRT_TIMER_7_INDEX
-#define PIC_IRT_UART_0_INDEX       9
-#define PIC_IRT_UART_1_INDEX       10
-#define PIC_IRT_I2C_0_INDEX       11
-#define PIC_IRT_I2C_1_INDEX       12
-#define PIC_IRT_PCMCIA_INDEX           13
-#define PIC_IRT_GPIO_INDEX             14
-#define PIC_IRT_HYPER_INDEX            15
-#define PIC_IRT_PCIX_INDEX             16
-#define PIC_IRT_GMAC0_INDEX            17
-#define PIC_IRT_GMAC1_INDEX            18
-#define PIC_IRT_GMAC2_INDEX            19
-#define PIC_IRT_GMAC3_INDEX            20
-#define PIC_IRT_XGS0_INDEX             21
-#define PIC_IRT_XGS1_INDEX             22
-#define PIC_IRT_HYPER_FATAL_INDEX      23
-#define PIC_IRT_PCIX_FATAL_INDEX       24
-#define PIC_IRT_BRIDGE_AERR_INDEX      25
-#define PIC_IRT_BRIDGE_BERR_INDEX     26
-#define PIC_IRT_BRIDGE_TB_INDEX        27
-#define PIC_IRT_BRIDGE_AERR_NMI_INDEX  28
+#define	PIC_IRT_WD_INDEX		0
+#define	PIC_IRT_TIMER_INDEX(i)		(1 + (i))
+#define	PIC_IRT_CLOCK_INDEX		PIC_IRT_TIMER_7_INDEX
+#define	PIC_IRT_UART_0_INDEX		9
+#define	PIC_IRT_UART_1_INDEX		10
+#define	PIC_IRT_I2C_0_INDEX		11
+#define	PIC_IRT_I2C_1_INDEX		12
+#define	PIC_IRT_PCMCIA_INDEX		13
+#define	PIC_IRT_GPIO_INDEX		14
+#define	PIC_IRT_HYPER_INDEX		15
+#define	PIC_IRT_PCIX_INDEX		16
+#define	PIC_IRT_GMAC0_INDEX		17
+#define	PIC_IRT_GMAC1_INDEX		18
+#define	PIC_IRT_GMAC2_INDEX		19
+#define	PIC_IRT_GMAC3_INDEX		20
+#define	PIC_IRT_XGS0_INDEX		21
+#define	PIC_IRT_XGS1_INDEX		22
+#define	PIC_IRT_HYPER_FATAL_INDEX	23
+#define	PIC_IRT_PCIX_FATAL_INDEX	24
+#define	PIC_IRT_BRIDGE_AERR_INDEX	25
+#define	PIC_IRT_BRIDGE_BERR_INDEX	26
+#define	PIC_IRT_BRIDGE_TB_INDEX		27
+#define	PIC_IRT_BRIDGE_AERR_NMI_INDEX	28
 
 /* numbering for XLS */
-#define PIC_IRT_BRIDGE_ERR_INDEX       25
-#define PIC_IRT_PCIE_LINK0_INDEX       26
-#define PIC_IRT_PCIE_LINK1_INDEX       27
-#define PIC_IRT_PCIE_LINK2_INDEX       23
-#define PIC_IRT_PCIE_LINK3_INDEX       24
-#define PIC_IRT_PCIE_INT_INDEX         28
-#define PIC_IRT_PCIE_FATAL_INDEX       29
-#define PIC_IRT_GPIO_B_INDEX           30
-#define PIC_IRT_USB_INDEX              31
-
-#define PIC_NUM_IRTS                   32
-
-#define PIC_SYS_TIMER_MAXVAL_0_BASE 0x100
-#define PIC_SYS_TIMER_MAXVAL_1_BASE 0x110
-
-#define PIC_SYS_TIMER_0_BASE 0x120
-#define PIC_SYS_TIMER_1_BASE 0x130
-
-#define PIC_CLOCK_TIMER 7
-
-#define PIC_CTRL    0x00
-#define PIC_IPI     0x04
-#define PIC_INT_ACK 0x06
-
-#define WD_MAX_VAL_0 0x08
-#define WD_MAX_VAL_1 0x09
-#define WD_MASK_0    0x0a
-#define WD_MASK_1    0x0b
-#define WD_HEARBEAT_0 0x0c
-#define WD_HEARBEAT_1 0x0d
-
-#define PIC_IRT_0_BASE 0x40
-#define PIC_IRT_1_BASE 0x80
-
-#define PIC_IRT_0_WD     (PIC_IRT_0_BASE   + PIC_IRT_WD_INDEX)
-#define PIC_IRT_1_WD     (PIC_IRT_1_BASE   + PIC_IRT_WD_INDEX)
-#define PIC_IRT_0_TIMER_0     (PIC_IRT_0_BASE   + PIC_IRT_TIMER_0_INDEX)
-#define PIC_IRT_1_TIMER_0     (PIC_IRT_1_BASE   + PIC_IRT_TIMER_0_INDEX)
-#define PIC_IRT_0_TIMER_1     (PIC_IRT_0_BASE   + PIC_IRT_TIMER_1_INDEX)
-#define PIC_IRT_1_TIMER_1     (PIC_IRT_1_BASE   + PIC_IRT_TIMER_1_INDEX)
-#define PIC_IRT_0_TIMER_2     (PIC_IRT_0_BASE   + PIC_IRT_TIMER_2_INDEX)
-#define PIC_IRT_1_TIMER_2     (PIC_IRT_1_BASE   + PIC_IRT_TIMER_2_INDEX)
-#define PIC_IRT_0_TIMER_3     (PIC_IRT_0_BASE   + PIC_IRT_TIMER_3_INDEX)
-#define PIC_IRT_1_TIMER_3     (PIC_IRT_1_BASE   + PIC_IRT_TIMER_3_INDEX)
-#define PIC_IRT_0_TIMER_4     (PIC_IRT_0_BASE   + PIC_IRT_TIMER_4_INDEX)
-#define PIC_IRT_1_TIMER_4     (PIC_IRT_1_BASE   + PIC_IRT_TIMER_4_INDEX)
-#define PIC_IRT_0_TIMER_5     (PIC_IRT_0_BASE   + PIC_IRT_TIMER_5_INDEX)
-#define PIC_IRT_1_TIMER_5     (PIC_IRT_1_BASE   + PIC_IRT_TIMER_5_INDEX)
-#define PIC_IRT_0_TIMER_6     (PIC_IRT_0_BASE   + PIC_IRT_TIMER_6_INDEX)
-#define PIC_IRT_1_TIMER_6     (PIC_IRT_1_BASE   + PIC_IRT_TIMER_6_INDEX)
-#define PIC_IRT_0_TIMER_7     (PIC_IRT_0_BASE   + PIC_IRT_TIMER_7_INDEX)
-#define PIC_IRT_1_TIMER_7     (PIC_IRT_1_BASE   + PIC_IRT_TIMER_7_INDEX)
-#define PIC_IRT_0_CLOCK       (PIC_IRT_0_TIMER_7)
-#define PIC_IRT_1_CLOCK       (PIC_IRT_1_TIMER_7)
-#define PIC_IRT_0_UART_0 (PIC_IRT_0_BASE + PIC_IRT_UART_0_INDEX)
-#define PIC_IRT_1_UART_0 (PIC_IRT_1_BASE + PIC_IRT_UART_0_INDEX)
-#define PIC_IRT_0_UART_1 (PIC_IRT_0_BASE + PIC_IRT_UART_1_INDEX)
-#define PIC_IRT_1_UART_1 (PIC_IRT_1_BASE + PIC_IRT_UART_1_INDEX)
-#define PIC_IRT_0_I2C_0 (PIC_IRT_0_BASE + PIC_IRT_I2C_0_INDEX)
-#define PIC_IRT_1_I2C_0 (PIC_IRT_1_BASE + PIC_IRT_I2C_0_INDEX)
-#define PIC_IRT_0_I2C_1 (PIC_IRT_0_BASE + PIC_IRT_I2C_1_INDEX)
-#define PIC_IRT_1_I2C_1 (PIC_IRT_1_BASE + PIC_IRT_I2C_1_INDEX)
-#define PIC_IRT_0_HYPER       (PIC_IRT_0_BASE + PIC_IRT_HYPER_INDEX)
-#define PIC_IRT_1_HYPER       (PIC_IRT_1_BASE + PIC_IRT_HYPER_INDEX)
-#define PIC_IRT_0_PCIX        (PIC_IRT_0_BASE + PIC_IRT_PCIX_INDEX)
-#define PIC_IRT_1_PCIX        (PIC_IRT_1_BASE + PIC_IRT_PCIX_INDEX)
-
-#define PIC_TIMER_0_MAXVAL_0   (PIC_SYS_TIMER_MAXVAL_0_BASE + 0)
-#define PIC_TIMER_0_MAXVAL_1   (PIC_SYS_TIMER_MAXVAL_1_BASE + 0)
-#define PIC_TIMER_0_COUNTER_0  (PIC_SYS_TIMER_0_BASE + 0)
-#define PIC_TIMER_0_COUNTER_1  (PIC_SYS_TIMER_1_BASE + 0)
-#define PIC_TIMER_6_MAXVAL_0   (PIC_SYS_TIMER_MAXVAL_0_BASE + 6)
-#define PIC_TIMER_6_MAXVAL_1   (PIC_SYS_TIMER_MAXVAL_1_BASE + 6)
-#define PIC_TIMER_6_COUNTER_0  (PIC_SYS_TIMER_0_BASE + 6)
-#define PIC_TIMER_6_COUNTER_1  (PIC_SYS_TIMER_1_BASE + 6)
-#define PIC_TIMER_7_MAXVAL_0   (PIC_SYS_TIMER_MAXVAL_0_BASE + 7)
-#define PIC_TIMER_7_MAXVAL_1   (PIC_SYS_TIMER_MAXVAL_1_BASE + 7)
-#define PIC_TIMER_7_COUNTER_0  (PIC_SYS_TIMER_0_BASE + 7)
-#define PIC_TIMER_7_COUNTER_1  (PIC_SYS_TIMER_1_BASE + 7)
-
-#define PIC_IRQ_BASE      8
-#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE
-#define PIC_WD_IRQ      (PIC_IRQ_BASE + PIC_IRT_WD_INDEX)
-#define PIC_TIMER_0_IRQ (PIC_IRQ_BASE + PIC_IRT_TIMER_0_INDEX)
-#define PIC_TIMER_1_IRQ (PIC_IRQ_BASE + PIC_IRT_TIMER_1_INDEX)
-#define PIC_TIMER_2_IRQ (PIC_IRQ_BASE + PIC_IRT_TIMER_2_INDEX)
-#define PIC_TIMER_3_IRQ (PIC_IRQ_BASE + PIC_IRT_TIMER_3_INDEX)
-#define PIC_TIMER_4_IRQ (PIC_IRQ_BASE + PIC_IRT_TIMER_4_INDEX)
-#define PIC_TIMER_5_IRQ (PIC_IRQ_BASE + PIC_IRT_TIMER_5_INDEX)
-#define PIC_TIMER_6_IRQ (PIC_IRQ_BASE + PIC_IRT_TIMER_6_INDEX)
-#define PIC_TIMER_7_IRQ (PIC_IRQ_BASE + PIC_IRT_TIMER_7_INDEX)
-#define PIC_CLOCK_IRQ   (PIC_TIMER_7_IRQ)
-#define PIC_UART_0_IRQ  (PIC_IRQ_BASE + PIC_IRT_UART_0_INDEX)
-#define PIC_UART_1_IRQ  (PIC_IRQ_BASE + PIC_IRT_UART_1_INDEX)
-#define PIC_I2C_0_IRQ   (PIC_IRQ_BASE + PIC_IRT_I2C_0_INDEX)
-#define PIC_I2C_1_IRQ   (PIC_IRQ_BASE + PIC_IRT_I2C_1_INDEX)
-#define PIC_PCMCIA_IRQ           (PIC_IRQ_BASE + PIC_IRT_PCMCIA_INDEX)
-#define PIC_GPIO_IRQ             (PIC_IRQ_BASE + PIC_IRT_GPIO_INDEX)
-#define PIC_HYPER_IRQ            (PIC_IRQ_BASE + PIC_IRT_HYPER_INDEX)
-#define PIC_PCIX_IRQ             (PIC_IRQ_BASE + PIC_IRT_PCIX_INDEX)
-#define PIC_GMAC_0_IRQ            (PIC_IRQ_BASE + PIC_IRT_GMAC0_INDEX)
-#define PIC_GMAC_1_IRQ            (PIC_IRQ_BASE + PIC_IRT_GMAC1_INDEX)
-#define PIC_GMAC_2_IRQ            (PIC_IRQ_BASE + PIC_IRT_GMAC2_INDEX)
-#define PIC_GMAC_3_IRQ            (PIC_IRQ_BASE + PIC_IRT_GMAC3_INDEX)
-#define PIC_XGS_0_IRQ             (PIC_IRQ_BASE + PIC_IRT_XGS0_INDEX)
-#define PIC_XGS_1_IRQ             (PIC_IRQ_BASE + PIC_IRT_XGS1_INDEX)
-#define PIC_HYPER_FATAL_IRQ      (PIC_IRQ_BASE + PIC_IRT_HYPER_FATAL_INDEX)
-#define PIC_PCIX_FATAL_IRQ       (PIC_IRQ_BASE + PIC_IRT_PCIX_FATAL_INDEX)
-#define PIC_BRIDGE_AERR_IRQ      (PIC_IRQ_BASE + PIC_IRT_BRIDGE_AERR_INDEX)
-#define PIC_BRIDGE_BERR_IRQ      (PIC_IRQ_BASE + PIC_IRT_BRIDGE_BERR_INDEX)
-#define PIC_BRIDGE_TB_IRQ        (PIC_IRQ_BASE + PIC_IRT_BRIDGE_TB_INDEX)
-#define PIC_BRIDGE_AERR_NMI_IRQ  (PIC_IRQ_BASE + PIC_IRT_BRIDGE_AERR_NMI_INDEX)
-
-#define PIC_BRIDGE_ERR_IRQ       (PIC_IRQ_BASE + PIC_IRT_BRIDGE_ERR_INDEX)
-#define PIC_PCIE_LINK0_IRQ       (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK0_INDEX)
-#define PIC_PCIE_LINK1_IRQ       (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK1_INDEX)
-#define PIC_PCIE_LINK2_IRQ       (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK2_INDEX)
-#define PIC_PCIE_LINK3_IRQ       (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK3_INDEX)
-#define PIC_PCIE_INT_IRQ         (PIC_IRQ_BASE + PIC_IRT_PCIE_INT__INDEX)
-#define PIC_PCIE_FATAL_IRQ       (PIC_IRQ_BASE + PIC_IRT_PCIE_FATAL_INDEX)
-#define PIC_GPIO_B_IRQ           (PIC_IRQ_BASE + PIC_IRT_GPIO_B_INDEX)
-#define PIC_USB_IRQ              (PIC_IRQ_BASE + PIC_IRT_USB_INDEX)
-
-#define PIC_IRT_LAST_IRQ         PIC_USB_IRQ
-
-#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) ( ((irq)>=PIC_TIMER_0_IRQ) && ((irq)<=PIC_TIMER_7_IRQ) )
-
-#define PIC_IRQ_IS_IRT(irq) ( ((irq)>=PIC_IRT_FIRST_IRQ) && ((irq)<=PIC_IRT_LAST_IRQ) )
-
+#define	PIC_IRT_BRIDGE_ERR_INDEX	25
+#define	PIC_IRT_PCIE_LINK0_INDEX	26
+#define	PIC_IRT_PCIE_LINK1_INDEX	27
+#define	PIC_IRT_PCIE_LINK2_INDEX	23
+#define	PIC_IRT_PCIE_LINK3_INDEX	24
+#define	PIC_IRT_PCIE_INT_INDEX		28
+#define	PIC_IRT_PCIE_FATAL_INDEX	29
+#define	PIC_IRT_GPIO_B_INDEX		30
+#define	PIC_IRT_USB_INDEX		31
+
+#define	PIC_NUM_IRTS			32
+
+#define	PIC_CLOCK_TIMER			7
+
+#define	PIC_CTRL			0x00
+#define	PIC_IPI				0x04
+#define	PIC_INT_ACK			0x06
+
+#define	WD_MAX_VAL_0			0x08
+#define	WD_MAX_VAL_1			0x09
+#define	WD_MASK_0			0x0a
+#define	WD_MASK_1			0x0b
+#define	WD_HEARBEAT_0			0x0c
+#define	WD_HEARBEAT_1			0x0d
+
+#define	PIC_IRT_0_BASE			0x40
+#define	PIC_IRT_1_BASE			0x80
+#define	PIC_TIMER_MAXVAL_0_BASE		0x100
+#define	PIC_TIMER_MAXVAL_1_BASE		0x110
+#define	PIC_TIMER_COUNT_0_BASE		0x120
+#define	PIC_TIMER_COUNT_1_BASE		0x130
+
+
+#define	PIC_IRT_0(picintr)	(PIC_IRT_0_BASE + (picintr))
+#define	PIC_IRT_1(picintr)	(PIC_IRT_1_BASE + (picintr))
+
+#define	PIC_TIMER_MAXVAL_0(i)	(PIC_TIMER_MAXVAL_0_BASE + (i))
+#define	PIC_TIMER_MAXVAL_1(i)	(PIC_TIMER_MAXVAL_1_BASE + (i))
+#define	PIC_TIMER_COUNT_0(i)	(PIC_TIMER_COUNT_0_BASE + (i))
+#define	PIC_TIMER_COUNT_1(i)	(PIC_TIMER_COUNT_0_BASE + (i))
+
+#define	PIC_IRQ_BASE		8
+#define	PIC_IRT_FIRST_IRQ	PIC_IRQ_BASE
+
+#define	PIC_WD_IRQ		(PIC_IRQ_BASE + PIC_IRT_WD_INDEX)
+#define	PIC_TIMER_IRQ(i)	(PIC_IRQ_BASE + PIC_IRT_TIMER_INDEX(i))
+#define	PIC_CLOCK_IRQ		PIC_TIMER_IRQ(PIC_CLOCK_TIMER)
+
+#define	PIC_UART_0_IRQ		(PIC_IRQ_BASE + PIC_IRT_UART_0_INDEX)
+#define	PIC_UART_1_IRQ		(PIC_IRQ_BASE + PIC_IRT_UART_1_INDEX)
+#define	PIC_I2C_0_IRQ		(PIC_IRQ_BASE + PIC_IRT_I2C_0_INDEX)
+#define	PIC_I2C_1_IRQ		(PIC_IRQ_BASE + PIC_IRT_I2C_1_INDEX)
+#define	PIC_PCMCIA_IRQ		(PIC_IRQ_BASE + PIC_IRT_PCMCIA_INDEX)
+#define	PIC_GPIO_IRQ		(PIC_IRQ_BASE + PIC_IRT_GPIO_INDEX)
+#define	PIC_HYPER_IRQ		(PIC_IRQ_BASE + PIC_IRT_HYPER_INDEX)
+#define	PIC_PCIX_IRQ		(PIC_IRQ_BASE + PIC_IRT_PCIX_INDEX)
+#define	PIC_GMAC_0_IRQ		(PIC_IRQ_BASE + PIC_IRT_GMAC0_INDEX)
+#define	PIC_GMAC_1_IRQ		(PIC_IRQ_BASE + PIC_IRT_GMAC1_INDEX)
+#define	PIC_GMAC_2_IRQ		(PIC_IRQ_BASE + PIC_IRT_GMAC2_INDEX)
+#define	PIC_GMAC_3_IRQ		(PIC_IRQ_BASE + PIC_IRT_GMAC3_INDEX)
+#define	PIC_XGS_0_IRQ		(PIC_IRQ_BASE + PIC_IRT_XGS0_INDEX)
+#define	PIC_XGS_1_IRQ		(PIC_IRQ_BASE + PIC_IRT_XGS1_INDEX)
+#define	PIC_HYPER_FATAL_IRQ	(PIC_IRQ_BASE + PIC_IRT_HYPER_FATAL_INDEX)
+#define	PIC_PCIX_FATAL_IRQ	(PIC_IRQ_BASE + PIC_IRT_PCIX_FATAL_INDEX)
+#define	PIC_BRIDGE_AERR_IRQ	(PIC_IRQ_BASE + PIC_IRT_BRIDGE_AERR_INDEX)
+#define	PIC_BRIDGE_BERR_IRQ	(PIC_IRQ_BASE + PIC_IRT_BRIDGE_BERR_INDEX)
+#define	PIC_BRIDGE_TB_IRQ	(PIC_IRQ_BASE + PIC_IRT_BRIDGE_TB_INDEX)
+#define	PIC_BRIDGE_AERR_NMI_IRQ	(PIC_IRQ_BASE + PIC_IRT_BRIDGE_AERR_NMI_INDEX)
+
+#define	PIC_BRIDGE_ERR_IRQ	(PIC_IRQ_BASE + PIC_IRT_BRIDGE_ERR_INDEX)
+#define	PIC_PCIE_LINK0_IRQ	(PIC_IRQ_BASE + PIC_IRT_PCIE_LINK0_INDEX)
+#define	PIC_PCIE_LINK1_IRQ	(PIC_IRQ_BASE + PIC_IRT_PCIE_LINK1_INDEX)
+#define	PIC_PCIE_LINK2_IRQ	(PIC_IRQ_BASE + PIC_IRT_PCIE_LINK2_INDEX)
+#define	PIC_PCIE_LINK3_IRQ	(PIC_IRQ_BASE + PIC_IRT_PCIE_LINK3_INDEX)
+#define	PIC_PCIE_INT_IRQ	(PIC_IRQ_BASE + PIC_IRT_PCIE_INT__INDEX)
+#define	PIC_PCIE_FATAL_IRQ	(PIC_IRQ_BASE + PIC_IRT_PCIE_FATAL_INDEX)
+#define	PIC_GPIO_B_IRQ		(PIC_IRQ_BASE + PIC_IRT_GPIO_B_INDEX)
+#define	PIC_USB_IRQ		(PIC_IRQ_BASE + PIC_IRT_USB_INDEX)
+
+#define	PIC_IRT_LAST_IRQ	PIC_USB_IRQ
+#define	PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_IRQ(0)) && ((irq) <= PIC_TIMER_IRQ(7)))
+#define	PIC_IRQ_IS_IRT(irq)	(((irq) >= PIC_IRT_FIRST_IRQ) && ((irq) <= PIC_IRT_LAST_IRQ))
 
 extern struct mtx xlr_pic_lock;
 
-
-static __inline__ __uint32_t 
-pic_read_control(int haslock)
+static __inline uint32_t 
+pic_read_control(void)
 {
 	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
-	__uint32_t reg;
+	uint32_t reg;
 
-	if ((rmi_spin_mutex_safe) && (haslock == 0))
-	  mtx_lock_spin(&xlr_pic_lock);
+	mtx_lock_spin(&xlr_pic_lock);
 	xlr_read_reg(mmio, PIC_CTRL);
-	if ((rmi_spin_mutex_safe) && (haslock == 0))
-	  mtx_unlock_spin(&xlr_pic_lock);
-	return reg;
+	mtx_unlock_spin(&xlr_pic_lock);
+	return (reg);
 }
 
-static __inline__ void 
-pic_write_control(__uint32_t control, int haslock)
+static __inline void 
+pic_write_control(uint32_t control)
 {
 	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
 
-	if ((rmi_spin_mutex_safe) && (haslock == 0))
-	  mtx_lock_spin(&xlr_pic_lock);
+	mtx_lock_spin(&xlr_pic_lock);
 	xlr_write_reg(mmio, PIC_CTRL, control);
-	if ((rmi_spin_mutex_safe) && (haslock == 0))
-	  mtx_unlock_spin(&xlr_pic_lock);
+	mtx_unlock_spin(&xlr_pic_lock);
 }
-static __inline__ void 
-pic_update_control(__uint32_t control, int haslock)
+
+static __inline void 
+pic_update_control(__uint32_t control)
 {
 	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
 
-	if ((rmi_spin_mutex_safe) && (haslock == 0))
-	  mtx_lock_spin(&xlr_pic_lock);
+	mtx_lock_spin(&xlr_pic_lock);
 	xlr_write_reg(mmio, PIC_CTRL, (control | xlr_read_reg(mmio, PIC_CTRL)));
-	if ((rmi_spin_mutex_safe) && (haslock == 0))
-	  mtx_unlock_spin(&xlr_pic_lock);
+	mtx_unlock_spin(&xlr_pic_lock);
 }
 
-static __inline__ void 
-pic_ack(int irq, int haslock)
+static __inline void 
+pic_ack(int irq)
 {
 	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
 
@@ -253,44 +188,51 @@ pic_ack(int irq, int haslock)
 		return;
 
 	if (PIC_IRQ_IS_EDGE_TRIGGERED(irq)) {
-	  if ((rmi_spin_mutex_safe) && (haslock == 0))
 		mtx_lock_spin(&xlr_pic_lock);
-	  xlr_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
-	  if ((rmi_spin_mutex_safe) && (haslock == 0))
+		xlr_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
 		mtx_unlock_spin(&xlr_pic_lock);
-		return;
 	}
 	return;
 }
 
-static inline void 
-pic_delayed_ack(int irq, int haslock)
+static __inline void 
+pic_delayed_ack(int irq)
 {
 	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
 
 	if (!PIC_IRQ_IS_IRT(irq))
 		return;
-
 	if (!PIC_IRQ_IS_EDGE_TRIGGERED(irq)) {
-		if ((rmi_spin_mutex_safe)&& (haslock == 0))
-		  mtx_lock_spin(&xlr_pic_lock);
+		mtx_lock_spin(&xlr_pic_lock);
 		xlr_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
-		if ((rmi_spin_mutex_safe) && (haslock == 0))
-		  mtx_unlock_spin(&xlr_pic_lock);
-		return;
+		mtx_unlock_spin(&xlr_pic_lock);
 	}
+	return;
 }
 
-static inline
-void pic_send_ipi(int cpu, int ipi, int haslock)
+static __inline
+void pic_send_ipi(int cpu, int ipi)
 {
-        xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
-        int tid, pid;
+	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
+	int tid, pid;
+
+	tid = cpu & 0x3;
+	pid = (cpu >> 2) & 0x7;
+	xlr_write_reg(mmio, PIC_IPI, (pid << 20) | (tid << 16) | ipi);
+}
 
-        tid = cpu & 0x3;
-        pid = (cpu >> 2) & 0x7;
+static __inline
+void pic_setup_intr(int picintr, int irq, uint32_t cpumask)
+{
+        xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
+	int level;
 
-	xlr_write_reg(mmio, PIC_IPI,  (pid << 20) | (tid << 16) | ipi);
+	mtx_lock_spin(&xlr_pic_lock);
+	level = PIC_IRQ_IS_EDGE_TRIGGERED(irq);
+	xlr_write_reg(mmio, PIC_IRT_0(picintr), cpumask);
+	xlr_write_reg(mmio, PIC_IRT_1(picintr), ((1 << 31) | (level << 30) |
+	    (1 << 6) | irq));
+	mtx_unlock_spin(&xlr_pic_lock);
 }
 
-#endif				/* _RMI_PIC_H_ */
+#endif	/* _RMI_PIC_H_ */

Modified: head/sys/mips/rmi/xlr_machdep.c
==============================================================================
--- head/sys/mips/rmi/xlr_machdep.c	Wed Aug 25 11:11:14 2010	(r211810)
+++ head/sys/mips/rmi/xlr_machdep.c	Wed Aug 25 11:49:48 2010	(r211811)
@@ -89,7 +89,6 @@ struct mtx xlr_pic_lock;
  * Parameters from boot loader
  */
 struct boot1_info xlr_boot1_info;
-struct xlr_loader_info xlr_loader_info;	/* FIXME : Unused */
 int xlr_run_mode;
 int xlr_argc;
 int32_t *xlr_argv, *xlr_envp;
@@ -574,8 +573,7 @@ void
 platform_ipi_send(int cpuid)
 {
 
-	pic_send_ipi(xlr_cpuid_to_hwtid[cpuid],
-	    platform_ipi_intrnum(), 0);
+	pic_send_ipi(xlr_cpuid_to_hwtid[cpuid], platform_ipi_intrnum());
 
 }
 

Modified: head/sys/mips/rmi/xlr_pci.c
==============================================================================
--- head/sys/mips/rmi/xlr_pci.c	Wed Aug 25 11:11:14 2010	(r211810)
+++ head/sys/mips/rmi/xlr_pci.c	Wed Aug 25 11:49:48 2010	(r211811)
@@ -122,6 +122,7 @@ static struct rman irq_rman, port_rman, 
 static void
 xlr_pci_init_resources(void)
 {
+
 	irq_rman.rm_start = 0;
 	irq_rman.rm_end = 255;
 	irq_rman.rm_type = RMAN_ARRAY;
@@ -150,6 +151,7 @@ xlr_pci_init_resources(void)
 static int
 xlr_pcib_probe(device_t dev)
 {
+
 	if (xlr_board_info.is_xls)
 		device_set_desc(dev, "XLS PCIe bus");
 	else
@@ -158,12 +160,13 @@ xlr_pcib_probe(device_t dev)
 	xlr_pci_init_resources();
 	xlr_pci_config_base = (void *)MIPS_PHYS_TO_KSEG1(DEFAULT_PCI_CONFIG_BASE);
 
-	return 0;
+	return (0);
 }
 
 static int
 xlr_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
 {
+
 	switch (which) {
 	case PCIB_IVAR_DOMAIN:
 		*result = 0;
@@ -190,14 +193,16 @@ xlr_pcib_write_ivar(device_t dev, device
 static int
 xlr_pcib_maxslots(device_t dev)
 {
+
 	return (PCI_SLOTMAX);
 }
 
 static __inline__ void 
 disable_and_clear_cache_error(void)
 {
-	uint64_t lsu_cfg0 = read_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CFG0_REGID);
+	uint64_t lsu_cfg0;
 
+	lsu_cfg0 = read_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CFG0_REGID);
 	lsu_cfg0 = lsu_cfg0 & ~0x2e;
 	write_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CFG0_REGID, lsu_cfg0);
 	/* Clear cache error log */
@@ -227,17 +232,17 @@ pci_cfg_read_32bit(uint32_t addr)
 	uint64_t cerr_cpu_log = 0;
 
 	disable_and_clear_cache_error();
-
 	temp = bswap32(*p);
 
 	/* Read cache err log */
-	cerr_cpu_log = read_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CERRLOG_REGID);
+	cerr_cpu_log = read_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU,
+	    LSU_CERRLOG_REGID);
 	if (cerr_cpu_log) {
 		/* Device don't exist. */
 		temp = ~0x0;
 	}
 	clear_and_enable_cache_error();
-	return temp;
+	return (temp);
 }
 
 static u_int32_t
@@ -258,7 +263,7 @@ xlr_pcib_read_config(device_t dev, u_int
 	else if (width == 2)
 		return ((data >> ((reg & 3) << 3)) & 0xffff);
 	else
-		return data;
+		return (data);
 }
 
 static void
@@ -294,14 +299,16 @@ xlr_pcib_write_config(device_t dev, u_in
 static int 
 xlr_pcib_attach(device_t dev)
 {
+
 	device_add_child(dev, "pci", 0);
 	bus_generic_attach(dev);
-	return 0;
+	return (0);
 }
 
 static void
 xlr_pcib_identify(driver_t * driver, device_t parent)
 {
+
 	if (xlr_board_info.is_xls) {
 		xlr_reg_t *pcie_mmio_le = xlr_io_mmio(XLR_IO_PCIE_1_OFFSET);
 		xlr_reg_t reg_link0 = xlr_read_reg(pcie_mmio_le, (0x80 >> 2));
@@ -325,14 +332,13 @@ xlr_alloc_msi(device_t pcib, device_t de
 	int i;
 	device_t parent, tmp;
 
-
 	/* find the lane on which the slot is connected to */
 	tmp = dev;
 	while (1) {
 		parent = device_get_parent(tmp);
 		if (parent == NULL || parent == pcib) {
 			device_printf(dev, "Cannot find parent bus\n");
-			return ENXIO;
+			return (ENXIO);
 		}
 		if (strcmp(device_get_nameunit(parent), "pci0") == 0)
 			break;
@@ -353,7 +359,7 @@ xlr_alloc_msi(device_t pcib, device_t de
 		pciirq = PIC_PCIE_LINK3_IRQ;
 		break;
 	default:
-		return ENXIO;
+		return (ENXIO);
 	}
 
 	irqs[0] = pciirq;
@@ -364,45 +370,49 @@ xlr_alloc_msi(device_t pcib, device_t de
 	for (i = 1; i < count; i++)
 		irqs[i] = pciirq + 64 * i;
 
-	return 0;
+	return (0);
 }
 
 static int
 xlr_release_msi(device_t pcib, device_t dev, int count, int *irqs)
 {
-	device_printf(dev, "%s: msi release %d\n", device_get_nameunit(pcib), count);
-	return 0;
+	device_printf(dev, "%s: msi release %d\n", device_get_nameunit(pcib),
+	    count);
+	return (0);
 }
 
 static int
-xlr_map_msi(device_t pcib, device_t dev, int irq, uint64_t * addr, uint32_t * data)
+xlr_map_msi(device_t pcib, device_t dev, int irq, uint64_t * addr,
+    uint32_t * data)
 {
+
 	switch (irq) {
-		case PIC_PCIE_LINK0_IRQ:
-		case PIC_PCIE_LINK1_IRQ:
-		case PIC_PCIE_LINK2_IRQ:
-		case PIC_PCIE_LINK3_IRQ:
+	case PIC_PCIE_LINK0_IRQ:
+	case PIC_PCIE_LINK1_IRQ:
+	case PIC_PCIE_LINK2_IRQ:
+	case PIC_PCIE_LINK3_IRQ:
 		*addr = MIPS_MSI_ADDR(0);
 		*data = MIPS_MSI_DATA(irq);
-		return 0;
+		return (0);
 
 	default:
-		device_printf(dev, "%s: map_msi for irq %d  - ignored", device_get_nameunit(pcib),
-		    irq);
+		device_printf(dev, "%s: map_msi for irq %d  - ignored", 
+		    device_get_nameunit(pcib), irq);
 		return (ENXIO);
 	}
-
 }
 
 static void
 bridge_pcix_ack(void *arg)
 {
+
 	xlr_read_reg(xlr_io_mmio(XLR_IO_PCIX_OFFSET), 0x140 >> 2);
 }
 
 static void
 bridge_pcix_mask_ack(void *arg)
 {
+
 	xlr_mask_hard_irq(arg);
 	bridge_pcix_ack(arg);
 }
@@ -415,20 +425,28 @@ bridge_pcie_ack(void *arg)
 	xlr_reg_t *pcie_mmio_le = xlr_io_mmio(XLR_IO_PCIE_1_OFFSET);
 
 	switch (irq) {
-	case PIC_PCIE_LINK0_IRQ : reg = PCIE_LINK0_MSI_STATUS; break;
-	case PIC_PCIE_LINK1_IRQ : reg = PCIE_LINK1_MSI_STATUS; break;
-	case PIC_PCIE_LINK2_IRQ : reg = PCIE_LINK2_MSI_STATUS; break;
-	case PIC_PCIE_LINK3_IRQ : reg = PCIE_LINK3_MSI_STATUS; break;
+	case PIC_PCIE_LINK0_IRQ:
+		reg = PCIE_LINK0_MSI_STATUS;
+		break;
+	case PIC_PCIE_LINK1_IRQ:
+		reg = PCIE_LINK1_MSI_STATUS;
+		break;
+	case PIC_PCIE_LINK2_IRQ:
+		reg = PCIE_LINK2_MSI_STATUS;
+		break;
+	case PIC_PCIE_LINK3_IRQ:
+		reg = PCIE_LINK3_MSI_STATUS;
+		break;
 	default:
 		return;
 	}
-
 	xlr_write_reg(pcie_mmio_le, reg>>2, 0xffffffff);
 }
 
 static void
 bridge_pcie_mask_ack(void *arg)
 {
+
 	xlr_mask_hard_irq(arg);
 	bridge_pcie_ack(arg);
 }
@@ -440,8 +458,6 @@ mips_platform_pci_setup_intr(device_t de
     driver_intr_t * intr, void *arg,
     void **cookiep)
 {
-	int level;
-	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
 	int error = 0;
 	int xlrirq;
 
@@ -451,43 +467,29 @@ mips_platform_pci_setup_intr(device_t de
 	if (rman_get_start(irq) != rman_get_end(irq)) {
 		device_printf(dev, "Interrupt allocation %lu != %lu\n",
 		    rman_get_start(irq), rman_get_end(irq));
-		return EINVAL;
+		return (EINVAL);
 	}
 	xlrirq = rman_get_start(irq);
 
 	if (strcmp(device_get_name(dev), "pcib") != 0)
-		return 0;
+		return (0);
 
 	if (xlr_board_info.is_xls == 0) {
-		if (rmi_spin_mutex_safe)
-			 mtx_lock_spin(&xlr_pic_lock);
-		level = PIC_IRQ_IS_EDGE_TRIGGERED(PIC_IRT_PCIX_INDEX);
-		xlr_write_reg(mmio, PIC_IRT_0_PCIX, 0x01);
-		xlr_write_reg(mmio, PIC_IRT_1_PCIX, ((1 << 31) | (level << 30) |
-		    (1 << 6) | (PIC_PCIX_IRQ)));
-		if (rmi_spin_mutex_safe)
-			 mtx_unlock_spin(&xlr_pic_lock);
 		xlr_cpu_establish_hardintr(device_get_name(child), filt,
 		    intr, arg, PIC_PCIX_IRQ, flags, cookiep,
 		    bridge_pcix_mask_ack, xlr_unmask_hard_irq,
 		    bridge_pcix_ack, NULL);
+		pic_setup_intr(PIC_IRT_PCIX_INDEX, PIC_PCIX_IRQ, 0x1);
 	} else {
-		if (rmi_spin_mutex_safe)
-			 mtx_lock_spin(&xlr_pic_lock);
-		xlr_write_reg(mmio, PIC_IRT_0_BASE + xlrirq - PIC_IRQ_BASE, 0x01);
-		xlr_write_reg(mmio, PIC_IRT_1_BASE + xlrirq - PIC_IRQ_BASE,
-		    ((1 << 31) | (1 << 30) | (1 << 6) | xlrirq));
-		if (rmi_spin_mutex_safe)
-			 mtx_unlock_spin(&xlr_pic_lock);
-
 		xlr_cpu_establish_hardintr(device_get_name(child), filt,
 		    intr, arg, xlrirq, flags, cookiep,
 	    	    bridge_pcie_mask_ack, xlr_unmask_hard_irq,
 		    bridge_pcie_ack, NULL);
+		pic_setup_intr(xlrirq - PIC_IRQ_BASE, xlrirq, 0x1);
 	}
 
-	return bus_generic_setup_intr(dev, child, irq, flags, filt, intr,
-	    arg, cookiep);
+	return (bus_generic_setup_intr(dev, child, irq, flags, filt, intr,
+	    arg, cookiep));
 }
 
 static int
@@ -498,7 +500,7 @@ mips_platform_pci_teardown_intr(device_t
 		/* if needed reprogram the pic to clear pcix related entry */
 		device_printf(dev, "teardown intr\n");
 	}
-	return bus_generic_teardown_intr(dev, child, irq, cookie);
+	return (bus_generic_teardown_intr(dev, child, irq, cookie));
 }
 
 static struct resource *
@@ -524,12 +526,12 @@ xlr_pci_alloc_resource(device_t bus, dev
 		break;
 
 	default:
-		return 0;
+		return (0);
 	}
 
 	rv = rman_reserve_resource(rm, start, end, count, flags, child);
 	if (rv == 0)
-		return 0;
+		return (0);
 
 	rman_set_rid(rv, *rid);
 
@@ -547,13 +549,14 @@ xlr_pci_alloc_resource(device_t bus, dev
 			return (NULL);
 		}
 	}
-	return rv;
+	return (rv);
 }
 
 static int
 xlr_pci_release_resource(device_t bus, device_t child, int type, int rid,
 		       struct resource *r)
 {
+
 	return (rman_release_resource(r));
 }
 
@@ -561,6 +564,7 @@ static int
 xlr_pci_activate_resource(device_t bus, device_t child, int type, int rid,
                       struct resource *r)
 {
+
 	return (rman_activate_resource(r));
 }
 
@@ -568,12 +572,14 @@ static int
 xlr_pci_deactivate_resource(device_t bus, device_t child, int type, int rid,
                           struct resource *r)
 {
+
 	return (rman_deactivate_resource(r));
 }
 
 static int
 mips_pci_route_interrupt(device_t bus, device_t dev, int pin)
 {
+
 	/*
 	 * Validate requested pin number.
 	 */
@@ -583,13 +589,13 @@ mips_pci_route_interrupt(device_t bus, d
 	if (xlr_board_info.is_xls) {
 		switch (pin) {
 		case 1:
-			return PIC_PCIE_LINK0_IRQ;
+			return (PIC_PCIE_LINK0_IRQ);
 		case 2:
-			return PIC_PCIE_LINK1_IRQ;
+			return (PIC_PCIE_LINK1_IRQ);
 		case 3:
-			return PIC_PCIE_LINK2_IRQ;
+			return (PIC_PCIE_LINK2_IRQ);
 		case 4:
-			return PIC_PCIE_LINK3_IRQ;
+			return (PIC_PCIE_LINK3_IRQ);
 		}
 	} else {
 		if (pin == 1) {



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