Date: Wed, 28 Sep 2011 15:36:08 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-user@freebsd.org Subject: svn commit: r225842 - user/adrian/if_ath_tx/sys/dev/ath/ath_hal/ar5416 Message-ID: <201109281536.p8SFa8Ig079429@svn.freebsd.org>
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Author: adrian Date: Wed Sep 28 15:36:08 2011 New Revision: 225842 URL: http://svn.freebsd.org/changeset/base/225842 Log: Flip back to the atheros defaults for now. Now that I've figured out why I'm getting performance issues on these mips boards (interrupts occuring in a race window between critical_enter and "wait", and thus being delayed until the next interrupt), this provides better RX performance under heavy UDP load. This doesn't fix the issue - it just means that under heavy UDP load, I'm not getting 1 RX interrupt every 2ms. This turns out not to be often enough in some occasional situations. Some more research is needed though.. Modified: user/adrian/if_ath_tx/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Modified: user/adrian/if_ath_tx/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c ============================================================================== --- user/adrian/if_ath_tx/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Wed Sep 28 15:01:20 2011 (r225841) +++ user/adrian/if_ath_tx/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Wed Sep 28 15:36:08 2011 (r225842) @@ -361,8 +361,8 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMO OS_REG_WRITE(ah, AR_MIRT, 0); #ifdef AH_AR5416_INTERRUPT_MITIGATION - OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); - OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); + OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 250); + OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 700); #endif ar5416InitBB(ah, chan);
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