Date: Sun, 6 Nov 2016 16:27:09 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r308375 - head/contrib/llvm/lib/Target/AArch64 Message-ID: <201611061627.uA6GR9YS038025@repo.freebsd.org>
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Author: dim Date: Sun Nov 6 16:27:09 2016 New Revision: 308375 URL: https://svnweb.freebsd.org/changeset/base/308375 Log: Pull in r278002 from upstream llvm trunk (by Silviu Baranga): [AArch64] PR28877: Don't assume we're running after legalization when creating vcvtfp2fxs Summary: The DAG combine transformation that was generating the aarch64_neon_vcvtfp2fxs node was assuming that all inputs where legal and wasn't accounting that the input could be a v4f64 if we're trying to do the transformation before legalization. We now bail out in this case. All illegal types besides v4f64 were already rejected. Fixes https://llvm.org/bugs/show_bug.cgi?id=28877 Reviewers: jmolloy Subscribers: aemerson, rengolin, llvm-commits Differential Revision: https://reviews.llvm.org/D23261 This fixes several ports on AArch64. Requested by: andrew MFC after: 3 days Modified: head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp Modified: head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp ============================================================================== --- head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp Sun Nov 6 15:25:46 2016 (r308374) +++ head/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp Sun Nov 6 16:27:09 2016 (r308375) @@ -7562,6 +7562,7 @@ static SDValue performIntToFpCombine(SDN /// Fold a floating-point multiply by power of two into floating-point to /// fixed-point conversion. static SDValue performFpToIntCombine(SDNode *N, SelectionDAG &DAG, + TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) { if (!Subtarget->hasNEON()) return SDValue(); @@ -7604,10 +7605,16 @@ static SDValue performFpToIntCombine(SDN ResTy = FloatBits == 32 ? MVT::v2i32 : MVT::v2i64; break; case 4: - ResTy = MVT::v4i32; + ResTy = FloatBits == 32 ? MVT::v4i32 : MVT::v4i64; break; } + if (ResTy == MVT::v4i64 && DCI.isBeforeLegalizeOps()) + return SDValue(); + + assert((ResTy != MVT::v4i64 || DCI.isBeforeLegalizeOps()) && + "Illegal vector type after legalization"); + SDLoc DL(N); bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT; unsigned IntrinsicOpcode = IsSigned ? Intrinsic::aarch64_neon_vcvtfp2fxs @@ -9711,7 +9718,7 @@ SDValue AArch64TargetLowering::PerformDA return performIntToFpCombine(N, DAG, Subtarget); case ISD::FP_TO_SINT: case ISD::FP_TO_UINT: - return performFpToIntCombine(N, DAG, Subtarget); + return performFpToIntCombine(N, DAG, DCI, Subtarget); case ISD::FDIV: return performFDivCombine(N, DAG, Subtarget); case ISD::OR:
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