Date: Sat, 9 Aug 2008 09:23:57 +0200 From: "Valerio Daelli" <valerio.daelli@gmail.com> To: freebsd-questions@freebsd.org Cc: ben@electricembers.net Subject: Re: Questions about coretemp Message-ID: <27dbfc8c0808090023p77d1984ckb90e27513ed3f2d4@mail.gmail.com> In-Reply-To: <Pine.BSF.4.64.0808081331590.16357@internal.electricembers.net> References: <200808072237.52918.pieter@degoeje.nl> <35145.1218148465@tristatelogic.com> <8cb6106e0808071623u7d1a6127x1b2f6ce2f472d233@mail.gmail.com> <Pine.BSF.4.64.0808071628040.83993@internal.electricembers.net> <27dbfc8c0808080319o5383a9faqb2f3d434f56677ea@mail.gmail.com> <Pine.BSF.4.64.0808081331590.16357@internal.electricembers.net>
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On Fri, Aug 8, 2008 at 10:35 PM, <ben@electricembers.net> wrote: >> >> have you checked your device.hints? >> Also there is the cpuid port which may help you identify if your CPU is >> supported. >> >> Valerio Daelli > > I'm not sure what I would be looking for in device.hints. Below is the output of cpuid. Perhaps Xeons are not supported by coretemp? :::::::::::::: > > eax in eax ebx ecx edx > 00000000 00000005 756e6547 6c65746e 49656e69 > 00000001 00000f4a 01020800 0000641d bfebfbff > 00000002 605b5001 00000000 00000000 007d7040 > 00000003 00000000 00000000 00000000 00000000 > 00000004 00004121 01c0003f 0000001f 00000000 > 00000005 00000040 00000040 00000000 00000000 > 80000000 80000008 00000000 00000000 00000000 > 80000001 00000000 00000000 00000001 20100000 > 80000002 20202020 20202020 20202020 20202020 > 80000003 6e492020 286c6574 58202952 286e6f65 > 80000004 20294d54 20555043 30302e33 007a4847 > 80000005 00000000 00000000 00000000 00000000 > 80000006 00000000 00000000 08006040 00000000 > 80000007 00000000 00000000 00000000 00000000 > 80000008 00003024 00000000 00000000 00000000 > > Vendor ID: "GenuineIntel"; CPUID level 5 > > Intel-specific functions: > Version 00000f4a: > Type 0 - Original OEM > Family 15 - Pentium 4 > Extended family 0 > Model 4 - Intel Pentium 4 processor (generic) or newer > Stepping 10 > Reserved 0 > > Extended brand string: " Intel(R) Xeon(TM) CPU 3.00GHz" > CLFLUSH instruction cache line size: 8 > Initial APIC ID: 1 > Hyper threading siblings: 2 > > Feature flags: bfebfbff: > FPU Floating Point Unit > VME Virtual 8086 Mode Enhancements > DE Debugging Extensions > PSE Page Size Extensions > TSC Time Stamp Counter > MSR Model Specific Registers > PAE Physical Address Extension > MCE Machine Check Exception > CX8 COMPXCHG8B Instruction > APIC On-chip Advanced Programmable Interrupt Controller present and enabled > SEP Fast System Call > MTRR Memory Type Range Registers > PGE PTE Global Flag > MCA Machine Check Architecture > CMOV Conditional Move and Compare Instructions > FGPAT Page Attribute Table > PSE-36 36-bit Page Size Extension > CLFSH CFLUSH instruction > DS Debug store > ACPI Thermal Monitor and Clock Ctrl > MMX MMX instruction set > FXSR Fast FP/MMX Streaming SIMD Extensions save/restore > SSE Streaming SIMD Extensions instruction set > SSE2 SSE2 extensions > SS Self Snoop > HT Hyper Threading > TM Thermal monitor > 31 reserved > > Feature flags set 2: 0000641d: > SSE3 SSE3 extensions > 2 - unknown feature > MONITOR MONITOR/MWAIT instructions > DS-CPL CPL Qualified Debug Store > CID Context ID > CX16 CMPXCHG16B > xTPR Send Task Priority messages > > Extended feature flags: 20100000: > XD-bit Execution Disable bit > EM64T Intel Extended Memory 64 Technology > > Extended feature flags set 2: 00000001: > 0 - unknown feature > > TLB and cache info: > 50: Instruction TLB: 4KB and 2MB or 4MB pages, 64 entries > 5b: Data TLB: 4KB and 4MB pages, fully assoc., 64 entries > 60: 1st-level data cache: 16-KB, 8-way set associative, sectored cache, 64-byte line size > 40: No 2nd-level cache, or if 2nd-level cache exists, no 3rd-level cache > 70: Trace cache: 12K-micro-op, 4-way set assoc > 7d: 2nd-level cache: 2-MB, 8-way set associative, 64-byte line size > Processor serial: 0000-0F4A-0000-0000-0000-0000 Only CPU with CPUID >= 6 seems supported. I found this link useful http://www.intel.com/software/products/documentation/vlin/mergedprojects/analyzer_ec/mergedprojects/reference_olh/mergedprojects/instructions/instruct32_hh/vc46.htm Bye Valerio Daelli
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