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Date:      Fri, 17 Sep 2010 02:14:22 +0000 (UTC)
From:      Neel Natu <neel@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r212776 - head/sys/mips/include
Message-ID:  <201009170214.o8H2EMNY015135@svn.freebsd.org>

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Author: neel
Date: Fri Sep 17 02:14:21 2010
New Revision: 212776
URL: http://svn.freebsd.org/changeset/base/212776

Log:
  Get rid of unused macros.

Modified:
  head/sys/mips/include/cpuregs.h

Modified: head/sys/mips/include/cpuregs.h
==============================================================================
--- head/sys/mips/include/cpuregs.h	Fri Sep 17 01:13:48 2010	(r212775)
+++ head/sys/mips/include/cpuregs.h	Fri Sep 17 02:14:21 2010	(r212776)
@@ -58,10 +58,6 @@
 #ifndef _MIPS_CPUREGS_H_
 #define	_MIPS_CPUREGS_H_
 
-#if defined(_KERNEL_OPT)
-#include "opt_cputype.h"
-#endif
-
 /*
  * Address space.
  * 32-bit mips CPUS partition their 32-bit address space into four segments:
@@ -71,8 +67,6 @@
  * kseg1   0xa0000000 - 0xbfffffff  Physical memory, uncached, unmapped
  * kseg2   0xc0000000 - 0xffffffff  kernel-virtual,  mapped
  *
- * mips1 physical memory is limited to 512Mbytes, which is
- * doubly mapped in kseg0 (cached) and kseg1 (uncached.)
  * Caching of mapped addresses is controlled by bits in the TLB entry.
  */
 
@@ -343,29 +337,6 @@
 #define	MIPS_SR_INT_IE		0x00010001		/* XXX */
 #endif
 
-/*
- * These definitions are for MIPS32 processors.
- */
-#define	MIPS32_SR_RP		0x08000000	/* reduced power mode */
-#define	MIPS32_SR_FR		0x04000000	/* 64-bit capable fpu */
-#define	MIPS32_SR_RE		0x02000000	/* reverse user endian */
-#define	MIPS32_SR_MX		0x01000000	/* MIPS64 */
-#define	MIPS32_SR_PX		0x00800000	/* MIPS64 */
-#define	MIPS32_SR_BEV		0x00400000	/* Use boot exception vector */
-#define	MIPS32_SR_TS		0x00200000	/* TLB multiple match */
-#define	MIPS32_SR_SOFT_RESET	0x00100000	/* soft reset occurred */
-#define	MIPS32_SR_NMI		0x00080000	/* NMI occurred */
-#define	MIPS32_SR_INT_MASK	0x0000ff00
-#define	MIPS32_SR_KX		0x00000080	/* MIPS64 */
-#define	MIPS32_SR_SX		0x00000040	/* MIPS64 */
-#define	MIPS32_SR_UX		0x00000020	/* MIPS64 */
-#define	MIPS32_SR_KSU_MASK	0x00000018	/* privilege mode */
-#define	MIPS32_SR_KSU_USER	0x00000010
-#define	MIPS32_SR_KSU_SUPER	0x00000008
-#define	MIPS32_SR_KSU_KERNEL	0x00000000
-#define	MIPS32_SR_ERL		0x00000004	/* error level */
-#define	MIPS32_SR_EXL		0x00000002	/* exception level */
-
 #define	MIPS_SR_SOFT_RESET	MIPS3_SR_SR
 #define	MIPS_SR_DIAG_CH		MIPS3_SR_DIAG_CH
 #define	MIPS_SR_DIAG_CE		MIPS3_SR_DIAG_CE



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