Date: Sun, 18 Jan 2015 14:14:48 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r277320 - in head: . contrib/llvm/include/llvm/Analysis contrib/llvm/include/llvm/CodeGen contrib/llvm/include/llvm/Target contrib/llvm/lib/Analysis contrib/llvm/lib/MC contrib/llvm/lib... Message-ID: <201501181414.t0IEEmYI055850@svn.freebsd.org>
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Author: dim Date: Sun Jan 18 14:14:47 2015 New Revision: 277320 URL: https://svnweb.freebsd.org/changeset/base/277320 Log: Upgrade our copy of clang and llvm to 3.5.1 release. This is a bugfix only release, no new features have been added. Please note that this version requires C++11 support to build; see UPDATING for more information. Release notes for llvm and clang can be found here: <http://llvm.org/releases/3.5.1/docs/ReleaseNotes.html>; <http://llvm.org/releases/3.5.1/tools/clang/docs/ReleaseNotes.html>; MFC after: 1 month X-MFC-With: 276479 Added: head/contrib/llvm/lib/Target/Mips/MipsABIInfo.cpp - copied unchanged from r277223, vendor/llvm/dist/lib/Target/Mips/MipsABIInfo.cpp head/contrib/llvm/lib/Target/Mips/MipsABIInfo.h - copied unchanged from r277223, vendor/llvm/dist/lib/Target/Mips/MipsABIInfo.h head/contrib/llvm/lib/Target/Mips/MipsCCState.cpp - copied unchanged from r277223, vendor/llvm/dist/lib/Target/Mips/MipsCCState.cpp head/contrib/llvm/lib/Target/Mips/MipsCCState.h - copied unchanged from r277223, vendor/llvm/dist/lib/Target/Mips/MipsCCState.h head/contrib/llvm/patches/patch-07-llvm-r216989-r216990-fix-movw-armv6.diff - copied unchanged from r277318, head/contrib/llvm/patches/patch-08-llvm-r216989-r216990-fix-movw-armv6.diff head/contrib/llvm/patches/patch-08-clang-r217410-i386-garbage-float.diff - copied unchanged from r277299, head/contrib/llvm/patches/patch-09-clang-r217410-i386-garbage-float.diff head/contrib/llvm/patches/patch-09-llvm-r221709-debug-oom.diff - copied unchanged from r277299, head/contrib/llvm/patches/patch-10-llvm-r221709-debug-oom.diff head/contrib/llvm/patches/patch-10-llvm-r222562-loop-rotate.diff - copied unchanged from r277299, head/contrib/llvm/patches/patch-11-llvm-r222562-loop-rotate.diff head/contrib/llvm/patches/patch-11-add-llvm-gvn-option.diff - copied unchanged from r277299, head/contrib/llvm/patches/patch-12-add-llvm-gvn-option.diff head/contrib/llvm/patches/patch-12-llvm-r218241-dwarf2-warning.diff - copied unchanged from r277299, head/contrib/llvm/patches/patch-13-llvm-r218241-dwarf2-warning.diff head/contrib/llvm/patches/patch-13-llvm-r215352-aarch64-dyn-loader.diff - copied unchanged from r277299, head/contrib/llvm/patches/patch-14-llvm-r215352-aarch64-dyn-loader.diff head/contrib/llvm/patches/patch-14-llvm-r216571-dynamiclib-usability.diff - copied unchanged from r277299, head/contrib/llvm/patches/patch-15-llvm-r216571-dynamiclib-usability.diff head/contrib/llvm/patches/patch-15-clang-r221900-freebsd-aarch64.diff - copied unchanged from r277299, head/contrib/llvm/patches/patch-16-clang-r221900-freebsd-aarch64.diff head/contrib/llvm/patches/patch-16-llvm-r222856-libapr-miscompile.diff - copied unchanged from r277299, head/contrib/llvm/patches/patch-17-llvm-r222856-libapr-miscompile.diff head/contrib/llvm/patches/patch-17-llvm-r214802-armv6-cp10-cp11.diff - copied unchanged from r277299, head/contrib/llvm/patches/patch-18-llvm-r214802-armv6-cp10-cp11.diff head/contrib/llvm/patches/patch-18-llvm-r215811-arm-fpu-directive.diff - copied unchanged from r277299, head/contrib/llvm/patches/patch-19-llvm-r215811-arm-fpu-directive.diff head/contrib/llvm/patches/patch-19-enable-armv6-clrex.diff - copied unchanged from r277299, head/contrib/llvm/patches/patch-20-enable-armv6-clrex.diff head/contrib/llvm/patches/patch-20-llvm-r223147-arm-cpu-directive.diff - copied unchanged from r277299, head/contrib/llvm/patches/patch-22-llvm-r223147-arm-cpu-directive.diff head/contrib/llvm/patches/patch-21-llvm-r221170-ppc-vaarg.diff - copied unchanged from r277299, head/contrib/llvm/patches/patch-23-llvm-r221170-ppc-vaarg.diff head/contrib/llvm/patches/patch-22-llvm-r221791-ppc-small-pic.diff - copied, changed from r277299, head/contrib/llvm/patches/patch-24-llvm-r221791-ppc-small-pic.diff head/contrib/llvm/patches/patch-23-llvm-r224415-ppc-local.diff - copied unchanged from r277299, head/contrib/llvm/patches/patch-25-llvm-r224415-ppc-local.diff head/contrib/llvm/patches/patch-24-llvm-r213890-ppc-eh_frame.diff - copied unchanged from r277299, head/contrib/llvm/patches/patch-26-llvm-r213890-ppc-eh_frame.diff head/contrib/llvm/patches/patch-25-llvm-r224890-ppc-ctr-tls-loop.diff - copied unchanged from r277299, head/contrib/llvm/patches/patch-28-llvm-r224890-ppc-ctr-tls-loop.diff head/contrib/llvm/patches/patch-26-clang-r213790-type_traits-crash.diff - copied unchanged from r277299, head/contrib/llvm/patches/patch-29-clang-r213790-type_traits-crash.diff head/contrib/llvm/patches/patch-27-llvm-r222587-arm-add-pc.diff - copied unchanged from r277299, head/contrib/llvm/patches/patch-30-llvm-r222587-arm-add-pc.diff head/contrib/llvm/patches/patch-28-llvm-r222292-aarch64-no-neon.diff - copied unchanged from r277299, head/contrib/llvm/patches/patch-31-llvm-r222292-aarch64-no-neon.diff Deleted: head/contrib/llvm/patches/patch-07-llvm-r213960-ppc32-tls.diff head/contrib/llvm/patches/patch-08-llvm-r216989-r216990-fix-movw-armv6.diff head/contrib/llvm/patches/patch-09-clang-r217410-i386-garbage-float.diff head/contrib/llvm/patches/patch-10-llvm-r221709-debug-oom.diff head/contrib/llvm/patches/patch-11-llvm-r222562-loop-rotate.diff head/contrib/llvm/patches/patch-12-add-llvm-gvn-option.diff head/contrib/llvm/patches/patch-13-llvm-r218241-dwarf2-warning.diff head/contrib/llvm/patches/patch-14-llvm-r215352-aarch64-dyn-loader.diff head/contrib/llvm/patches/patch-15-llvm-r216571-dynamiclib-usability.diff head/contrib/llvm/patches/patch-16-clang-r221900-freebsd-aarch64.diff head/contrib/llvm/patches/patch-17-llvm-r222856-libapr-miscompile.diff head/contrib/llvm/patches/patch-18-llvm-r214802-armv6-cp10-cp11.diff head/contrib/llvm/patches/patch-19-llvm-r215811-arm-fpu-directive.diff head/contrib/llvm/patches/patch-20-enable-armv6-clrex.diff head/contrib/llvm/patches/patch-21-llvm-r223171-fix-vectorizer.diff head/contrib/llvm/patches/patch-22-llvm-r223147-arm-cpu-directive.diff head/contrib/llvm/patches/patch-23-llvm-r221170-ppc-vaarg.diff head/contrib/llvm/patches/patch-24-llvm-r221791-ppc-small-pic.diff head/contrib/llvm/patches/patch-25-llvm-r224415-ppc-local.diff head/contrib/llvm/patches/patch-26-llvm-r213890-ppc-eh_frame.diff head/contrib/llvm/patches/patch-27-llvm-r221703-ppc-tls_get_addr.diff head/contrib/llvm/patches/patch-28-llvm-r224890-ppc-ctr-tls-loop.diff head/contrib/llvm/patches/patch-29-clang-r213790-type_traits-crash.diff head/contrib/llvm/patches/patch-30-llvm-r222587-arm-add-pc.diff head/contrib/llvm/patches/patch-31-llvm-r222292-aarch64-no-neon.diff Modified: head/ObsoleteFiles.inc head/UPDATING head/contrib/llvm/include/llvm/Analysis/AliasSetTracker.h head/contrib/llvm/include/llvm/CodeGen/CallingConvLower.h head/contrib/llvm/include/llvm/Target/TargetCallingConv.td head/contrib/llvm/lib/Analysis/AliasSetTracker.cpp head/contrib/llvm/lib/Analysis/BlockFrequencyInfoImpl.cpp head/contrib/llvm/lib/Analysis/ValueTracking.cpp head/contrib/llvm/lib/MC/MCObjectFileInfo.cpp head/contrib/llvm/lib/Target/ARM/ARMFrameLowering.cpp head/contrib/llvm/lib/Target/ARM/ARMFrameLowering.h head/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp head/contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp head/contrib/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp head/contrib/llvm/lib/Target/Mips/Mips.td head/contrib/llvm/lib/Target/Mips/Mips16ISelLowering.cpp head/contrib/llvm/lib/Target/Mips/Mips16ISelLowering.h head/contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td head/contrib/llvm/lib/Target/Mips/MipsAsmPrinter.cpp head/contrib/llvm/lib/Target/Mips/MipsCallingConv.td head/contrib/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp head/contrib/llvm/lib/Target/Mips/MipsISelLowering.cpp head/contrib/llvm/lib/Target/Mips/MipsISelLowering.h head/contrib/llvm/lib/Target/Mips/MipsInstrFPU.td head/contrib/llvm/lib/Target/Mips/MipsInstrInfo.td head/contrib/llvm/lib/Target/Mips/MipsLongBranch.cpp head/contrib/llvm/lib/Target/Mips/MipsRegisterInfo.cpp head/contrib/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp head/contrib/llvm/lib/Target/Mips/MipsSEISelLowering.cpp head/contrib/llvm/lib/Target/Mips/MipsSEISelLowering.h head/contrib/llvm/lib/Target/Mips/MipsSubtarget.cpp head/contrib/llvm/lib/Target/Mips/MipsSubtarget.h head/contrib/llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp head/contrib/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp head/contrib/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp head/contrib/llvm/lib/Target/PowerPC/PPCFastISel.cpp head/contrib/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp head/contrib/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp head/contrib/llvm/lib/Target/PowerPC/PPCISelLowering.cpp head/contrib/llvm/lib/Target/PowerPC/PPCInstr64Bit.td head/contrib/llvm/lib/Target/PowerPC/PPCRegisterInfo.td head/contrib/llvm/lib/Target/X86/X86FastISel.cpp head/contrib/llvm/lib/Transforms/Scalar/IndVarSimplify.cpp head/contrib/llvm/lib/Transforms/Scalar/MergedLoadStoreMotion.cpp head/contrib/llvm/lib/Transforms/Scalar/SROA.cpp head/contrib/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp head/contrib/llvm/patches/README.TXT head/contrib/llvm/tools/clang/include/clang/Basic/DiagnosticSemaKinds.td head/contrib/llvm/tools/clang/lib/Basic/Version.cpp head/contrib/llvm/tools/clang/lib/CodeGen/CGExprScalar.cpp head/contrib/llvm/tools/clang/lib/CodeGen/TargetInfo.cpp head/contrib/llvm/tools/clang/lib/Sema/SemaDecl.cpp head/contrib/llvm/tools/clang/lib/Sema/SemaTemplate.cpp head/contrib/llvm/utils/TableGen/CallingConvEmitter.cpp head/etc/mtree/BSD.debug.dist head/etc/mtree/BSD.include.dist head/etc/mtree/BSD.usr.dist head/lib/clang/include/Makefile head/lib/clang/include/clang/Basic/Version.inc head/lib/clang/include/clang/Config/config.h head/lib/clang/include/llvm/Config/config.h head/lib/clang/libllvmmipscodegen/Makefile head/lib/libclang_rt/Makefile.inc head/tools/build/mk/OptionalObsoleteFiles.inc Directory Properties: head/contrib/llvm/ (props changed) head/contrib/llvm/tools/clang/ (props changed) Modified: head/ObsoleteFiles.inc ============================================================================== --- head/ObsoleteFiles.inc Sun Jan 18 14:04:55 2015 (r277319) +++ head/ObsoleteFiles.inc Sun Jan 18 14:14:47 2015 (r277320) @@ -38,6 +38,60 @@ # xargs -n1 | sort | uniq -d; # done +# 20150118: new clang import which bumps version from 3.5.0 to 3.5.1. +OLD_FILES+=usr/include/clang/3.5.0/__wmmintrin_aes.h +OLD_FILES+=usr/include/clang/3.5.0/__wmmintrin_pclmul.h +OLD_FILES+=usr/include/clang/3.5.0/altivec.h +OLD_FILES+=usr/include/clang/3.5.0/ammintrin.h +OLD_FILES+=usr/include/clang/3.5.0/arm_acle.h +OLD_FILES+=usr/include/clang/3.5.0/arm_neon.h +OLD_FILES+=usr/include/clang/3.5.0/avx2intrin.h +OLD_FILES+=usr/include/clang/3.5.0/avxintrin.h +OLD_FILES+=usr/include/clang/3.5.0/bmi2intrin.h +OLD_FILES+=usr/include/clang/3.5.0/bmiintrin.h +OLD_FILES+=usr/include/clang/3.5.0/cpuid.h +OLD_FILES+=usr/include/clang/3.5.0/emmintrin.h +OLD_FILES+=usr/include/clang/3.5.0/f16cintrin.h +OLD_FILES+=usr/include/clang/3.5.0/fma4intrin.h +OLD_FILES+=usr/include/clang/3.5.0/fmaintrin.h +OLD_FILES+=usr/include/clang/3.5.0/ia32intrin.h +OLD_FILES+=usr/include/clang/3.5.0/immintrin.h +OLD_FILES+=usr/include/clang/3.5.0/lzcntintrin.h +OLD_FILES+=usr/include/clang/3.5.0/mm3dnow.h +OLD_FILES+=usr/include/clang/3.5.0/mm_malloc.h +OLD_FILES+=usr/include/clang/3.5.0/mmintrin.h +OLD_FILES+=usr/include/clang/3.5.0/module.modulemap +OLD_FILES+=usr/include/clang/3.5.0/nmmintrin.h +OLD_FILES+=usr/include/clang/3.5.0/pmmintrin.h +OLD_FILES+=usr/include/clang/3.5.0/popcntintrin.h +OLD_FILES+=usr/include/clang/3.5.0/prfchwintrin.h +OLD_FILES+=usr/include/clang/3.5.0/rdseedintrin.h +OLD_FILES+=usr/include/clang/3.5.0/rtmintrin.h +OLD_FILES+=usr/include/clang/3.5.0/shaintrin.h +OLD_FILES+=usr/include/clang/3.5.0/smmintrin.h +OLD_FILES+=usr/include/clang/3.5.0/tbmintrin.h +OLD_FILES+=usr/include/clang/3.5.0/tmmintrin.h +OLD_FILES+=usr/include/clang/3.5.0/wmmintrin.h +OLD_FILES+=usr/include/clang/3.5.0/x86intrin.h +OLD_FILES+=usr/include/clang/3.5.0/xmmintrin.h +OLD_FILES+=usr/include/clang/3.5.0/xopintrin.h +OLD_DIRS+=usr/include/clang/3.5.0 +OLD_FILES+=usr/lib/clang/3.5.0/lib/freebsd/libclang_rt.asan-i386.a +OLD_FILES+=usr/lib/clang/3.5.0/lib/freebsd/libclang_rt.asan-x86_64.a +OLD_FILES+=usr/lib/clang/3.5.0/lib/freebsd/libclang_rt.asan_cxx-i386.a +OLD_FILES+=usr/lib/clang/3.5.0/lib/freebsd/libclang_rt.asan_cxx-x86_64.a +OLD_FILES+=usr/lib/clang/3.5.0/lib/freebsd/libclang_rt.profile-arm.a +OLD_FILES+=usr/lib/clang/3.5.0/lib/freebsd/libclang_rt.profile-i386.a +OLD_FILES+=usr/lib/clang/3.5.0/lib/freebsd/libclang_rt.profile-x86_64.a +OLD_FILES+=usr/lib/clang/3.5.0/lib/freebsd/libclang_rt.san-i386.a +OLD_FILES+=usr/lib/clang/3.5.0/lib/freebsd/libclang_rt.san-x86_64.a +OLD_FILES+=usr/lib/clang/3.5.0/lib/freebsd/libclang_rt.ubsan-i386.a +OLD_FILES+=usr/lib/clang/3.5.0/lib/freebsd/libclang_rt.ubsan-x86_64.a +OLD_FILES+=usr/lib/clang/3.5.0/lib/freebsd/libclang_rt.ubsan_cxx-i386.a +OLD_FILES+=usr/lib/clang/3.5.0/lib/freebsd/libclang_rt.ubsan_cxx-x86_64.a +OLD_DIRS+=usr/lib/clang/3.5.0/lib/freebsd +OLD_DIRS+=usr/lib/clang/3.5.0/lib +OLD_DIRS+=usr/lib/clang/3.5.0 # 20150102: removal of texinfo OLD_FILES+=usr/bin/info OLD_FILES+=usr/bin/infokey Modified: head/UPDATING ============================================================================== --- head/UPDATING Sun Jan 18 14:04:55 2015 (r277319) +++ head/UPDATING Sun Jan 18 14:14:47 2015 (r277320) @@ -31,6 +31,12 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 11 disable the most expensive debugging functionality run "ln -s 'abort:false,junk:false' /etc/malloc.conf".) +20150118: + Clang and llvm have been upgraded to 3.5.1 release. This is a bugfix + only release, no new features have been added. Please see the 20141231 + entry below for information about prerequisites and upgrading, if you + are not already using 3.5.0. + 20150107: ELF tools addr2line, elfcopy (strip), nm, size, and strings are now taken from the ELF Tool Chain project rather than GNU binutils. They Modified: head/contrib/llvm/include/llvm/Analysis/AliasSetTracker.h ============================================================================== --- head/contrib/llvm/include/llvm/Analysis/AliasSetTracker.h Sun Jan 18 14:04:55 2015 (r277319) +++ head/contrib/llvm/include/llvm/Analysis/AliasSetTracker.h Sun Jan 18 14:14:47 2015 (r277320) @@ -253,13 +253,16 @@ private: const MDNode *TBAAInfo, bool KnownMustAlias = false); void addUnknownInst(Instruction *I, AliasAnalysis &AA); - void removeUnknownInst(Instruction *I) { + void removeUnknownInst(AliasSetTracker &AST, Instruction *I) { + bool WasEmpty = UnknownInsts.empty(); for (size_t i = 0, e = UnknownInsts.size(); i != e; ++i) if (UnknownInsts[i] == I) { UnknownInsts[i] = UnknownInsts.back(); UnknownInsts.pop_back(); --i; --e; // Revisit the moved entry. } + if (!WasEmpty && UnknownInsts.empty()) + dropRef(AST); } void setVolatile() { Volatile = true; } Modified: head/contrib/llvm/include/llvm/CodeGen/CallingConvLower.h ============================================================================== --- head/contrib/llvm/include/llvm/CodeGen/CallingConvLower.h Sun Jan 18 14:04:55 2015 (r277319) +++ head/contrib/llvm/include/llvm/CodeGen/CallingConvLower.h Sun Jan 18 14:14:47 2015 (r277320) @@ -31,18 +31,25 @@ class TargetRegisterInfo; class CCValAssign { public: enum LocInfo { - Full, // The value fills the full location. - SExt, // The value is sign extended in the location. - ZExt, // The value is zero extended in the location. - AExt, // The value is extended with undefined upper bits. - BCvt, // The value is bit-converted in the location. - VExt, // The value is vector-widened in the location. - // FIXME: Not implemented yet. Code that uses AExt to mean - // vector-widen should be fixed to use VExt instead. - FPExt, // The floating-point value is fp-extended in the location. - Indirect // The location contains pointer to the value. + Full, // The value fills the full location. + SExt, // The value is sign extended in the location. + ZExt, // The value is zero extended in the location. + AExt, // The value is extended with undefined upper bits. + BCvt, // The value is bit-converted in the location. + VExt, // The value is vector-widened in the location. + // FIXME: Not implemented yet. Code that uses AExt to mean + // vector-widen should be fixed to use VExt instead. + FPExt, // The floating-point value is fp-extended in the location. + Indirect, // The location contains pointer to the value. + SExtUpper, // The value is in the upper bits of the location and should be + // sign extended when retrieved. + ZExtUpper, // The value is in the upper bits of the location and should be + // zero extended when retrieved. + AExtUpper // The value is in the upper bits of the location and should be + // extended with undefined upper bits when retrieved. // TODO: a subset of the value is in the location. }; + private: /// ValNo - This is the value number begin assigned (e.g. an argument number). unsigned ValNo; @@ -146,6 +153,9 @@ public: return (HTP == AExt || HTP == SExt || HTP == ZExt); } + bool isUpperBitsInLoc() const { + return HTP == AExtUpper || HTP == SExtUpper || HTP == ZExtUpper; + } }; /// CCAssignFn - This function assigns a location for Val, updating State to @@ -208,10 +218,10 @@ private: // while "%t" goes to the stack: it wouldn't be described in ByValRegs. // // Supposed use-case for this collection: - // 1. Initially ByValRegs is empty, InRegsParamsProceed is 0. + // 1. Initially ByValRegs is empty, InRegsParamsProcessed is 0. // 2. HandleByVal fillups ByValRegs. // 3. Argument analysis (LowerFormatArguments, for example). After - // some byval argument was analyzed, InRegsParamsProceed is increased. + // some byval argument was analyzed, InRegsParamsProcessed is increased. struct ByValInfo { ByValInfo(unsigned B, unsigned E, bool IsWaste = false) : Begin(B), End(E), Waste(IsWaste) {} @@ -229,9 +239,9 @@ private: }; SmallVector<ByValInfo, 4 > ByValRegs; - // InRegsParamsProceed - shows how many instances of ByValRegs was proceed + // InRegsParamsProcessed - shows how many instances of ByValRegs was proceed // during argument analysis. - unsigned InRegsParamsProceed; + unsigned InRegsParamsProcessed; protected: ParmContext CallOrPrologue; @@ -412,7 +422,7 @@ public: unsigned getInRegsParamsCount() const { return ByValRegs.size(); } // Returns count of byval in-regs arguments proceed. - unsigned getInRegsParamsProceed() const { return InRegsParamsProceed; } + unsigned getInRegsParamsProcessed() const { return InRegsParamsProcessed; } // Get information about N-th byval parameter that is stored in registers. // Here "ByValParamIndex" is N. @@ -436,20 +446,20 @@ public: // Returns false, if end is reached. bool nextInRegsParam() { unsigned e = ByValRegs.size(); - if (InRegsParamsProceed < e) - ++InRegsParamsProceed; - return InRegsParamsProceed < e; + if (InRegsParamsProcessed < e) + ++InRegsParamsProcessed; + return InRegsParamsProcessed < e; } // Clear byval registers tracking info. void clearByValRegsInfo() { - InRegsParamsProceed = 0; + InRegsParamsProcessed = 0; ByValRegs.clear(); } // Rewind byval registers tracking info. void rewindByValRegsInfo() { - InRegsParamsProceed = 0; + InRegsParamsProcessed = 0; } ParmContext getCallOrPrologue() const { return CallOrPrologue; } Modified: head/contrib/llvm/include/llvm/Target/TargetCallingConv.td ============================================================================== --- head/contrib/llvm/include/llvm/Target/TargetCallingConv.td Sun Jan 18 14:04:55 2015 (r277319) +++ head/contrib/llvm/include/llvm/Target/TargetCallingConv.td Sun Jan 18 14:14:47 2015 (r277320) @@ -67,6 +67,9 @@ class CCIfSplit<CCAction A> : CCIf<"ArgF /// the specified action. class CCIfSRet<CCAction A> : CCIf<"ArgFlags.isSRet()", A> {} +/// CCIfVarArg - If the current function is vararg - apply the action +class CCIfVarArg<CCAction A> : CCIf<"State.isVarArg()", A> {} + /// CCIfNotVarArg - If the current function is not vararg - apply the action class CCIfNotVarArg<CCAction A> : CCIf<"!State.isVarArg()", A> {} @@ -119,6 +122,12 @@ class CCPromoteToType<ValueType destTy> ValueType DestTy = destTy; } +/// CCPromoteToUpperBitsInType - If applied, this promotes the specified current +/// value to the specified type and shifts the value into the upper bits. +class CCPromoteToUpperBitsInType<ValueType destTy> : CCAction { + ValueType DestTy = destTy; +} + /// CCBitConvertToType - If applied, this bitconverts the specified current /// value to the specified type. class CCBitConvertToType<ValueType destTy> : CCAction { @@ -141,6 +150,13 @@ class CCDelegateTo<CallingConv cc> : CCA /// that the target supports. class CallingConv<list<CCAction> actions> { list<CCAction> Actions = actions; + bit Custom = 0; +} + +/// CustomCallingConv - An instance of this is used to declare calling +/// conventions that are implemented using a custom function of the same name. +class CustomCallingConv : CallingConv<[]> { + let Custom = 1; } /// CalleeSavedRegs - A list of callee saved registers for a given calling Modified: head/contrib/llvm/lib/Analysis/AliasSetTracker.cpp ============================================================================== --- head/contrib/llvm/lib/Analysis/AliasSetTracker.cpp Sun Jan 18 14:04:55 2015 (r277319) +++ head/contrib/llvm/lib/Analysis/AliasSetTracker.cpp Sun Jan 18 14:14:47 2015 (r277320) @@ -55,10 +55,13 @@ void AliasSet::mergeSetIn(AliasSet &AS, AliasTy = MayAlias; } + bool ASHadUnknownInsts = !AS.UnknownInsts.empty(); if (UnknownInsts.empty()) { // Merge call sites... - if (!AS.UnknownInsts.empty()) + if (ASHadUnknownInsts) { std::swap(UnknownInsts, AS.UnknownInsts); - } else if (!AS.UnknownInsts.empty()) { + addRef(); + } + } else if (ASHadUnknownInsts) { UnknownInsts.insert(UnknownInsts.end(), AS.UnknownInsts.begin(), AS.UnknownInsts.end()); AS.UnknownInsts.clear(); } @@ -76,6 +79,8 @@ void AliasSet::mergeSetIn(AliasSet &AS, AS.PtrListEnd = &AS.PtrList; assert(*AS.PtrListEnd == nullptr && "End of list is not null?"); } + if (ASHadUnknownInsts) + AS.dropRef(AST); } void AliasSetTracker::removeAliasSet(AliasSet *AS) { @@ -123,6 +128,8 @@ void AliasSet::addPointer(AliasSetTracke } void AliasSet::addUnknownInst(Instruction *I, AliasAnalysis &AA) { + if (UnknownInsts.empty()) + addRef(); UnknownInsts.push_back(I); if (!I->mayWriteToMemory()) { @@ -218,13 +225,14 @@ AliasSet *AliasSetTracker::findAliasSetF uint64_t Size, const MDNode *TBAAInfo) { AliasSet *FoundSet = nullptr; - for (iterator I = begin(), E = end(); I != E; ++I) { - if (I->Forward || !I->aliasesPointer(Ptr, Size, TBAAInfo, AA)) continue; + for (iterator I = begin(), E = end(); I != E;) { + iterator Cur = I++; + if (Cur->Forward || !Cur->aliasesPointer(Ptr, Size, TBAAInfo, AA)) continue; if (!FoundSet) { // If this is the first alias set ptr can go into. - FoundSet = I; // Remember it. + FoundSet = Cur; // Remember it. } else { // Otherwise, we must merge the sets. - FoundSet->mergeSetIn(*I, *this); // Merge in contents. + FoundSet->mergeSetIn(*Cur, *this); // Merge in contents. } } @@ -246,14 +254,14 @@ bool AliasSetTracker::containsPointer(Va AliasSet *AliasSetTracker::findAliasSetForUnknownInst(Instruction *Inst) { AliasSet *FoundSet = nullptr; - for (iterator I = begin(), E = end(); I != E; ++I) { - if (I->Forward || !I->aliasesUnknownInst(Inst, AA)) + for (iterator I = begin(), E = end(); I != E;) { + iterator Cur = I++; + if (Cur->Forward || !Cur->aliasesUnknownInst(Inst, AA)) continue; - if (!FoundSet) // If this is the first alias set ptr can go into. - FoundSet = I; // Remember it. - else if (!I->Forward) // Otherwise, we must merge the sets. - FoundSet->mergeSetIn(*I, *this); // Merge in contents. + FoundSet = Cur; // Remember it. + else if (!Cur->Forward) // Otherwise, we must merge the sets. + FoundSet->mergeSetIn(*Cur, *this); // Merge in contents. } return FoundSet; } @@ -393,6 +401,8 @@ void AliasSetTracker::add(const AliasSet /// tracker. void AliasSetTracker::remove(AliasSet &AS) { // Drop all call sites. + if (!AS.UnknownInsts.empty()) + AS.dropRef(*this); AS.UnknownInsts.clear(); // Clear the alias set. @@ -489,10 +499,10 @@ void AliasSetTracker::deleteValue(Value if (Instruction *Inst = dyn_cast<Instruction>(PtrVal)) { if (Inst->mayReadOrWriteMemory()) { // Scan all the alias sets to see if this call site is contained. - for (iterator I = begin(), E = end(); I != E; ++I) { - if (I->Forward) continue; - - I->removeUnknownInst(Inst); + for (iterator I = begin(), E = end(); I != E;) { + iterator Cur = I++; + if (!Cur->Forward) + Cur->removeUnknownInst(*this, Inst); } } } Modified: head/contrib/llvm/lib/Analysis/BlockFrequencyInfoImpl.cpp ============================================================================== --- head/contrib/llvm/lib/Analysis/BlockFrequencyInfoImpl.cpp Sun Jan 18 14:04:55 2015 (r277319) +++ head/contrib/llvm/lib/Analysis/BlockFrequencyInfoImpl.cpp Sun Jan 18 14:14:47 2015 (r277320) @@ -14,7 +14,7 @@ #include "llvm/Analysis/BlockFrequencyInfoImpl.h" #include "llvm/ADT/SCCIterator.h" #include "llvm/Support/raw_ostream.h" -#include <deque> +#include <numeric> using namespace llvm; using namespace llvm::bfi_detail; @@ -123,8 +123,12 @@ static void combineWeight(Weight &W, con } assert(W.Type == OtherW.Type); assert(W.TargetNode == OtherW.TargetNode); - assert(W.Amount < W.Amount + OtherW.Amount && "Unexpected overflow"); - W.Amount += OtherW.Amount; + assert(OtherW.Amount && "Expected non-zero weight"); + if (W.Amount > W.Amount + OtherW.Amount) + // Saturate on overflow. + W.Amount = UINT64_MAX; + else + W.Amount += OtherW.Amount; } static void combineWeightsBySorting(WeightList &Weights) { // Sort so edges to the same node are adjacent. @@ -207,11 +211,19 @@ void Distribution::normalize() { Shift = 33 - countLeadingZeros(Total); // Early exit if nothing needs to be scaled. - if (!Shift) + if (!Shift) { + // If we didn't overflow then combineWeights() shouldn't have changed the + // sum of the weights, but let's double-check. + assert(Total == std::accumulate(Weights.begin(), Weights.end(), UINT64_C(0), + [](uint64_t Sum, const Weight &W) { + return Sum + W.Amount; + }) && + "Expected total to be correct"); return; + } // Recompute the total through accumulation (rather than shifting it) so that - // it's accurate after shifting. + // it's accurate after shifting and any changes combineWeights() made above. Total = 0; // Sum the weights to each node and shift right if necessary. Modified: head/contrib/llvm/lib/Analysis/ValueTracking.cpp ============================================================================== --- head/contrib/llvm/lib/Analysis/ValueTracking.cpp Sun Jan 18 14:04:55 2015 (r277319) +++ head/contrib/llvm/lib/Analysis/ValueTracking.cpp Sun Jan 18 14:14:47 2015 (r277320) @@ -1987,23 +1987,31 @@ bool llvm::isSafeToSpeculativelyExecute( default: return true; case Instruction::UDiv: - case Instruction::URem: - // x / y is undefined if y == 0, but calculations like x / 3 are safe. - return isKnownNonZero(Inst->getOperand(1), TD); + case Instruction::URem: { + // x / y is undefined if y == 0. + const APInt *V; + if (match(Inst->getOperand(1), m_APInt(V))) + return *V != 0; + return false; + } case Instruction::SDiv: case Instruction::SRem: { - Value *Op = Inst->getOperand(1); - // x / y is undefined if y == 0 - if (!isKnownNonZero(Op, TD)) - return false; - // x / y might be undefined if y == -1 - unsigned BitWidth = getBitWidth(Op->getType(), TD); - if (BitWidth == 0) - return false; - APInt KnownZero(BitWidth, 0); - APInt KnownOne(BitWidth, 0); - computeKnownBits(Op, KnownZero, KnownOne, TD); - return !!KnownZero; + // x / y is undefined if y == 0 or x == INT_MIN and y == -1 + const APInt *X, *Y; + if (match(Inst->getOperand(1), m_APInt(Y))) { + if (*Y != 0) { + if (*Y == -1) { + // The numerator can't be MinSignedValue if the denominator is -1. + if (match(Inst->getOperand(0), m_APInt(X))) + return !Y->isMinSignedValue(); + // The numerator *might* be MinSignedValue. + return false; + } + // The denominator is not 0 or -1, it's safe to proceed. + return true; + } + } + return false; } case Instruction::Load: { const LoadInst *LI = cast<LoadInst>(Inst); Modified: head/contrib/llvm/lib/MC/MCObjectFileInfo.cpp ============================================================================== --- head/contrib/llvm/lib/MC/MCObjectFileInfo.cpp Sun Jan 18 14:04:55 2015 (r277319) +++ head/contrib/llvm/lib/MC/MCObjectFileInfo.cpp Sun Jan 18 14:14:47 2015 (r277320) @@ -341,6 +341,8 @@ void MCObjectFileInfo::InitELFMCObjectFi break; case Triple::mips: case Triple::mipsel: + case Triple::mips64: + case Triple::mips64el: // MIPS uses indirect pointer to refer personality functions, so that the // eh_frame section can be read-only. DW.ref.personality will be generated // for relocation. Modified: head/contrib/llvm/lib/Target/ARM/ARMFrameLowering.cpp ============================================================================== --- head/contrib/llvm/lib/Target/ARM/ARMFrameLowering.cpp Sun Jan 18 14:04:55 2015 (r277319) +++ head/contrib/llvm/lib/Target/ARM/ARMFrameLowering.cpp Sun Jan 18 14:14:47 2015 (r277320) @@ -566,11 +566,59 @@ void ARMFrameLowering::emitPrologue(Mach AFI->setShouldRestoreSPFromFP(true); } +// Resolve TCReturn pseudo-instruction +void ARMFrameLowering::fixTCReturn(MachineFunction &MF, + MachineBasicBlock &MBB) const { + MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); + assert(MBBI->isReturn() && "Can only insert epilog into returning blocks"); + unsigned RetOpcode = MBBI->getOpcode(); + DebugLoc dl = MBBI->getDebugLoc(); + const ARMBaseInstrInfo &TII = + *MF.getTarget().getSubtarget<ARMSubtarget>().getInstrInfo(); + + if (!(RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri)) + return; + + // Tail call return: adjust the stack pointer and jump to callee. + MBBI = MBB.getLastNonDebugInstr(); + MachineOperand &JumpTarget = MBBI->getOperand(0); + + // Jump to label or value in register. + if (RetOpcode == ARM::TCRETURNdi) { + unsigned TCOpcode = STI.isThumb() ? + (STI.isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) : + ARM::TAILJMPd; + MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); + if (JumpTarget.isGlobal()) + MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), + JumpTarget.getTargetFlags()); + else { + assert(JumpTarget.isSymbol()); + MIB.addExternalSymbol(JumpTarget.getSymbolName(), + JumpTarget.getTargetFlags()); + } + + // Add the default predicate in Thumb mode. + if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0); + } else if (RetOpcode == ARM::TCRETURNri) { + BuildMI(MBB, MBBI, dl, + TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)). + addReg(JumpTarget.getReg(), RegState::Kill); + } + + MachineInstr *NewMI = std::prev(MBBI); + for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i) + NewMI->addOperand(MBBI->getOperand(i)); + + // Delete the pseudo instruction TCRETURN. + MBB.erase(MBBI); + MBBI = NewMI; +} + void ARMFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); assert(MBBI->isReturn() && "Can only insert epilog into returning blocks"); - unsigned RetOpcode = MBBI->getOpcode(); DebugLoc dl = MBBI->getDebugLoc(); MachineFrameInfo *MFI = MF.getFrameInfo(); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); @@ -588,8 +636,10 @@ void ARMFrameLowering::emitEpilogue(Mach // All calls are tail calls in GHC calling conv, and functions have no // prologue/epilogue. - if (MF.getFunction()->getCallingConv() == CallingConv::GHC) + if (MF.getFunction()->getCallingConv() == CallingConv::GHC) { + fixTCReturn(MF, MBB); return; + } if (!AFI->hasStackFrame()) { if (NumBytes - ArgRegsSaveSize != 0) @@ -661,42 +711,7 @@ void ARMFrameLowering::emitEpilogue(Mach if (AFI->getGPRCalleeSavedArea1Size()) MBBI++; } - if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri) { - // Tail call return: adjust the stack pointer and jump to callee. - MBBI = MBB.getLastNonDebugInstr(); - MachineOperand &JumpTarget = MBBI->getOperand(0); - - // Jump to label or value in register. - if (RetOpcode == ARM::TCRETURNdi) { - unsigned TCOpcode = STI.isThumb() ? - (STI.isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) : - ARM::TAILJMPd; - MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); - if (JumpTarget.isGlobal()) - MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), - JumpTarget.getTargetFlags()); - else { - assert(JumpTarget.isSymbol()); - MIB.addExternalSymbol(JumpTarget.getSymbolName(), - JumpTarget.getTargetFlags()); - } - - // Add the default predicate in Thumb mode. - if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0); - } else if (RetOpcode == ARM::TCRETURNri) { - BuildMI(MBB, MBBI, dl, - TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)). - addReg(JumpTarget.getReg(), RegState::Kill); - } - - MachineInstr *NewMI = std::prev(MBBI); - for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i) - NewMI->addOperand(MBBI->getOperand(i)); - - // Delete the pseudo instruction TCRETURN. - MBB.erase(MBBI); - MBBI = NewMI; - } + fixTCReturn(MF, MBB); if (ArgRegsSaveSize) emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize); Modified: head/contrib/llvm/lib/Target/ARM/ARMFrameLowering.h ============================================================================== --- head/contrib/llvm/lib/Target/ARM/ARMFrameLowering.h Sun Jan 18 14:04:55 2015 (r277319) +++ head/contrib/llvm/lib/Target/ARM/ARMFrameLowering.h Sun Jan 18 14:14:47 2015 (r277320) @@ -31,6 +31,8 @@ public: void emitPrologue(MachineFunction &MF) const override; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; + void fixTCReturn(MachineFunction &MF, MachineBasicBlock &MBB) const; + bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, Modified: head/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp ============================================================================== --- head/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp Sun Jan 18 14:04:55 2015 (r277319) +++ head/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp Sun Jan 18 14:14:47 2015 (r277320) @@ -1521,7 +1521,7 @@ ARMTargetLowering::LowerCall(TargetLower // True if this byval aggregate will be split between registers // and memory. unsigned ByValArgsCount = CCInfo.getInRegsParamsCount(); - unsigned CurByValIdx = CCInfo.getInRegsParamsProceed(); + unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed(); if (CurByValIdx < ByValArgsCount) { @@ -2962,7 +2962,7 @@ ARMTargetLowering::LowerFormalArguments( if (Flags.isByVal()) { unsigned ExtraArgRegsSize; unsigned ExtraArgRegsSaveSize; - computeRegArea(CCInfo, MF, CCInfo.getInRegsParamsProceed(), + computeRegArea(CCInfo, MF, CCInfo.getInRegsParamsProcessed(), Flags.getByValSize(), ExtraArgRegsSize, ExtraArgRegsSaveSize); @@ -3086,7 +3086,7 @@ ARMTargetLowering::LowerFormalArguments( // Since they could be overwritten by lowering of arguments in case of // a tail call. if (Flags.isByVal()) { - unsigned CurByValIndex = CCInfo.getInRegsParamsProceed(); + unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed(); ByValStoreOffset = RoundUpToAlignment(ByValStoreOffset, Flags.getByValAlign()); int FrameIndex = StoreByValRegs( Modified: head/contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp ============================================================================== --- head/contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Sun Jan 18 14:04:55 2015 (r277319) +++ head/contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Sun Jan 18 14:14:47 2015 (r277320) @@ -200,14 +200,14 @@ class MipsAsmParser : public MCTargetAsm // Example: INSERT.B $w0[n], $1 => 16 > n >= 0 bool validateMSAIndex(int Val, int RegKind); - void setFeatureBits(unsigned Feature, StringRef FeatureString) { + void setFeatureBits(uint64_t Feature, StringRef FeatureString) { if (!(STI.getFeatureBits() & Feature)) { setAvailableFeatures( ComputeAvailableFeatures(STI.ToggleFeature(FeatureString))); } } - void clearFeatureBits(unsigned Feature, StringRef FeatureString) { + void clearFeatureBits(uint64_t Feature, StringRef FeatureString) { if (STI.getFeatureBits() & Feature) { setAvailableFeatures( ComputeAvailableFeatures(STI.ToggleFeature(FeatureString))); Modified: head/contrib/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp ============================================================================== --- head/contrib/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Sun Jan 18 14:04:55 2015 (r277319) +++ head/contrib/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Sun Jan 18 14:14:47 2015 (r277320) @@ -250,6 +250,11 @@ static DecodeStatus DecodeMem(MCInst &In uint64_t Address, const void *Decoder); +static DecodeStatus DecodeCacheOp(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); @@ -267,6 +272,14 @@ static DecodeStatus DecodeFMem(MCInst &I uint64_t Address, const void *Decoder); +static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, @@ -451,7 +464,7 @@ static DecodeStatus DecodeAddiGroupBranc InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2; + InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; bool HasRs = false; if (Rs >= Rt) { @@ -490,7 +503,7 @@ static DecodeStatus DecodeDaddiGroupBran InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2; + InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; bool HasRs = false; if (Rs >= Rt) { @@ -530,7 +543,7 @@ static DecodeStatus DecodeBlezlGroupBran InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2; + InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; bool HasRs = false; if (Rt == 0) @@ -575,7 +588,7 @@ static DecodeStatus DecodeBgtzlGroupBran InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2; + InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; if (Rt == 0) return MCDisassembler::Fail; @@ -617,7 +630,7 @@ static DecodeStatus DecodeBgtzGroupBranc InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2; + InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; bool HasRs = false; bool HasRt = false; @@ -666,7 +679,7 @@ static DecodeStatus DecodeBlezGroupBranc InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2; + InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; bool HasRs = false; if (Rt == 0) @@ -964,6 +977,23 @@ static DecodeStatus DecodeMem(MCInst &In return MCDisassembler::Success; } +static DecodeStatus DecodeCacheOp(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + int Offset = SignExtend32<16>(Insn & 0xffff); + unsigned Hint = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + + Inst.addOperand(MCOperand::CreateReg(Base)); + Inst.addOperand(MCOperand::CreateImm(Offset)); + Inst.addOperand(MCOperand::CreateImm(Hint)); + + return MCDisassembler::Success; +} + static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); @@ -995,15 +1025,15 @@ static DecodeStatus DecodeMSA128Mem(MCIn break; case Mips::LD_H: case Mips::ST_H: - Inst.addOperand(MCOperand::CreateImm(Offset << 1)); + Inst.addOperand(MCOperand::CreateImm(Offset * 2)); break; case Mips::LD_W: case Mips::ST_W: - Inst.addOperand(MCOperand::CreateImm(Offset << 2)); + Inst.addOperand(MCOperand::CreateImm(Offset * 4)); break; case Mips::LD_D: case Mips::ST_D: - Inst.addOperand(MCOperand::CreateImm(Offset << 3)); + Inst.addOperand(MCOperand::CreateImm(Offset * 8)); break; } @@ -1067,6 +1097,42 @@ static DecodeStatus DecodeFMem(MCInst &I return MCDisassembler::Success; } +static DecodeStatus DecodeFMem2(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + int Offset = SignExtend32<16>(Insn & 0xffff); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + + Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::CreateReg(Base)); + Inst.addOperand(MCOperand::CreateImm(Offset)); + + return MCDisassembler::Success; +} + +static DecodeStatus DecodeFMem3(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + int Offset = SignExtend32<16>(Insn & 0xffff); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + + Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::CreateReg(Base)); + Inst.addOperand(MCOperand::CreateImm(Offset)); + + return MCDisassembler::Success; +} + static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, @@ -1225,7 +1291,7 @@ static DecodeStatus DecodeBranchTarget(M unsigned Offset, uint64_t Address, const void *Decoder) { - int32_t BranchOffset = (SignExtend32<16>(Offset) << 2) + 4; + int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; Inst.addOperand(MCOperand::CreateImm(BranchOffset)); return MCDisassembler::Success; } @@ -1244,7 +1310,7 @@ static DecodeStatus DecodeBranchTarget21 unsigned Offset, uint64_t Address, const void *Decoder) { - int32_t BranchOffset = SignExtend32<21>(Offset) << 2; + int32_t BranchOffset = SignExtend32<21>(Offset) * 4; Inst.addOperand(MCOperand::CreateImm(BranchOffset)); return MCDisassembler::Success; @@ -1254,7 +1320,7 @@ static DecodeStatus DecodeBranchTarget26 unsigned Offset, uint64_t Address, const void *Decoder) { - int32_t BranchOffset = SignExtend32<26>(Offset) << 2; + int32_t BranchOffset = SignExtend32<26>(Offset) * 4; Inst.addOperand(MCOperand::CreateImm(BranchOffset)); return MCDisassembler::Success; @@ -1264,7 +1330,7 @@ static DecodeStatus DecodeBranchTargetMM unsigned Offset, uint64_t Address, const void *Decoder) { - int32_t BranchOffset = SignExtend32<16>(Offset) << 1; + int32_t BranchOffset = SignExtend32<16>(Offset) * 2; Inst.addOperand(MCOperand::CreateImm(BranchOffset)); return MCDisassembler::Success; } @@ -1317,12 +1383,12 @@ static DecodeStatus DecodeExtSize(MCInst static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { - Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) << 2)); + Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4)); return MCDisassembler::Success; } static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { - Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) << 3)); + Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8)); return MCDisassembler::Success; } Modified: head/contrib/llvm/lib/Target/Mips/Mips.td ============================================================================== --- head/contrib/llvm/lib/Target/Mips/Mips.td Sun Jan 18 14:04:55 2015 (r277319) +++ head/contrib/llvm/lib/Target/Mips/Mips.td Sun Jan 18 14:14:47 2015 (r277320) @@ -57,6 +57,8 @@ def MipsInstrInfo : InstrInfo; // Mips Subtarget features // //===----------------------------------------------------------------------===// +def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true", + "Disable SVR4-style position-independent code.">; def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", "General Purpose Registers are 64-bit wide.">; def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", @@ -67,13 +69,13 @@ def FeatureNaN2008 : SubtargetFeatur "IEEE 754-2008 NaN encoding.">; def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", "true", "Only supports single precision float">; -def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32", +def FeatureO32 : SubtargetFeature<"o32", "ABI", "MipsABIInfo::O32()", "Enable o32 ABI">; -def FeatureN32 : SubtargetFeature<"n32", "MipsABI", "N32", +def FeatureN32 : SubtargetFeature<"n32", "ABI", "MipsABIInfo::N32()", "Enable n32 ABI">; -def FeatureN64 : SubtargetFeature<"n64", "MipsABI", "N64", +def FeatureN64 : SubtargetFeature<"n64", "ABI", "MipsABIInfo::N64()", "Enable n64 ABI">; -def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI", +def FeatureEABI : SubtargetFeature<"eabi", "ABI", "MipsABIInfo::EABI()", "Enable eabi ABI">; def FeatureNoOddSPReg : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false", "Disable odd numbered single-precision " Modified: head/contrib/llvm/lib/Target/Mips/Mips16ISelLowering.cpp ============================================================================== --- head/contrib/llvm/lib/Target/Mips/Mips16ISelLowering.cpp Sun Jan 18 14:04:55 2015 (r277319) +++ head/contrib/llvm/lib/Target/Mips/Mips16ISelLowering.cpp Sun Jan 18 14:14:47 2015 (r277320) @@ -241,10 +241,9 @@ Mips16TargetLowering::EmitInstrWithCusto } } -bool Mips16TargetLowering:: -isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, - unsigned NextStackOffset, - const MipsFunctionInfo& FI) const { +bool Mips16TargetLowering::isEligibleForTailCallOptimization( + const CCState &CCInfo, unsigned NextStackOffset, + const MipsFunctionInfo &FI) const { // No tail call optimization for mips16. return false; } Modified: head/contrib/llvm/lib/Target/Mips/Mips16ISelLowering.h ============================================================================== --- head/contrib/llvm/lib/Target/Mips/Mips16ISelLowering.h Sun Jan 18 14:04:55 2015 (r277319) +++ head/contrib/llvm/lib/Target/Mips/Mips16ISelLowering.h Sun Jan 18 14:14:47 2015 (r277320) @@ -30,9 +30,9 @@ namespace llvm { MachineBasicBlock *MBB) const override; private: - bool isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, - unsigned NextStackOffset, - const MipsFunctionInfo& FI) const override; + bool isEligibleForTailCallOptimization( + const CCState &CCInfo, unsigned NextStackOffset, + const MipsFunctionInfo &FI) const override; void setMips16HardFloatLibCalls(); Modified: head/contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td ============================================================================== --- head/contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td Sun Jan 18 14:04:55 2015 (r277319) +++ head/contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td Sun Jan 18 14:14:47 2015 (r277320) @@ -419,6 +419,10 @@ defm : SetgePats<GPR64, SLT64, SLTu64>; defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>; // truncate +def : MipsPat<(trunc (assertsext GPR64:$src)), + (EXTRACT_SUBREG GPR64:$src, sub_32)>; +def : MipsPat<(trunc (assertzext GPR64:$src)), + (EXTRACT_SUBREG GPR64:$src, sub_32)>; def : MipsPat<(i32 (trunc GPR64:$src)), (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>; Copied: head/contrib/llvm/lib/Target/Mips/MipsABIInfo.cpp (from r277223, vendor/llvm/dist/lib/Target/Mips/MipsABIInfo.cpp) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/contrib/llvm/lib/Target/Mips/MipsABIInfo.cpp Sun Jan 18 14:14:47 2015 (r277320, copy of r277223, vendor/llvm/dist/lib/Target/Mips/MipsABIInfo.cpp) @@ -0,0 +1,45 @@ +//===---- MipsABIInfo.cpp - Information about MIPS ABI's ------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "MipsABIInfo.h" +#include "MipsRegisterInfo.h" + +using namespace llvm; + +namespace { +static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3}; + +static const MCPhysReg Mips64IntRegs[8] = { + Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, + Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64}; +} + +const ArrayRef<MCPhysReg> MipsABIInfo::GetByValArgRegs() const { + if (IsO32()) + return makeArrayRef(O32IntRegs); + if (IsN32() || IsN64()) + return makeArrayRef(Mips64IntRegs); + llvm_unreachable("Unhandled ABI"); +} + +const ArrayRef<MCPhysReg> MipsABIInfo::GetVarArgRegs() const { + if (IsO32()) + return makeArrayRef(O32IntRegs); + if (IsN32() || IsN64()) + return makeArrayRef(Mips64IntRegs); + llvm_unreachable("Unhandled ABI"); +} + +unsigned MipsABIInfo::GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const { + if (IsO32()) + return CC != CallingConv::Fast ? 16 : 0; + if (IsN32() || IsN64() || IsEABI()) + return 0; + llvm_unreachable("Unhandled ABI"); +} Copied: head/contrib/llvm/lib/Target/Mips/MipsABIInfo.h (from r277223, vendor/llvm/dist/lib/Target/Mips/MipsABIInfo.h) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/contrib/llvm/lib/Target/Mips/MipsABIInfo.h Sun Jan 18 14:14:47 2015 (r277320, copy of r277223, vendor/llvm/dist/lib/Target/Mips/MipsABIInfo.h) @@ -0,0 +1,61 @@ +//===---- MipsABIInfo.h - Information about MIPS ABI's --------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef MIPSABIINFO_H +#define MIPSABIINFO_H + +#include "llvm/ADT/ArrayRef.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/IR/CallingConv.h" + +namespace llvm { + +class MipsABIInfo { +public: + enum class ABI { Unknown, O32, N32, N64, EABI }; + +protected: + ABI ThisABI; + *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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