Date: Tue, 19 Mar 2013 13:57:19 +0900 From: YongHyeon PYUN <pyunyh@gmail.com> To: Michael BlackHeart <amdmiek@gmail.com> Cc: freebsd-stable <freebsd-stable@freebsd.org> Subject: Re: A few problems Message-ID: <20130319045719.GB1437@michelle.cdnetworks.com> In-Reply-To: <20130319045629.GA1437@michelle.cdnetworks.com> References: <CA%2BAz77Pyr=uAss7vW_54DNDm485yHaEu6Z4DvsF7iPLkWO2TiQ@mail.gmail.com> <20130318065938.GB1459@michelle.cdnetworks.com> <CA%2BAz77MX294tqnm%2Btm1KfnK6EV6wBK05OSr=A%2BZwzv2SMf8qaw@mail.gmail.com> <20130319045629.GA1437@michelle.cdnetworks.com>
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On Tue, Mar 19, 2013 at 01:56:29PM +0900, YongHyeon PYUN wrote:
> On Mon, Mar 18, 2013 at 05:19:11PM +0400, Michael BlackHeart wrote:
> > 2013/3/18 YongHyeon PYUN <pyunyh@gmail.com>:
> > > On Sat, Mar 16, 2013 at 01:08:06PM +0400, Michael BlackHeart wrote:
> > >> Hello there. I've got a couple of things I don't get or can't handle.
> > >>
> > >
> > > [...]
> > >
> > >> re0@pci0:4:0:0: class=0x020000 card=0x512c1462 chip=0x816810ec rev=0x02 hdr=0x00
> > >> vendor = 'Realtek Semiconductor Co., Ltd.'
> > >> device = 'RTL8111/8168B PCI Express Gigabit Ethernet controller'
> > >> class = network
> > >> subclass = ethernet
> > >> bar [10] = type I/O Port, range 32, base 0xd800, size 256, enabled
> > >> bar [18] = type Memory, range 64, base 0xfeaff000, size 4096, enabled
> > >> bar [20] = type Prefetchable Memory, range 64, base 0xf8ff0000,
> > >> size 65536, enabled
> > >> cap 01[40] = powerspec 3 supports D0 D1 D2 D3 current D0
> > >> cap 05[50] = MSI supports 1 message, 64 bit
> > >> cap 10[70] = PCI-Express 1 endpoint IRQ 1 max data 128(256) link x1(x1)
> > >> speed 2.5(2.5)
> > >> cap 11[b0] = MSI-X supports 2 messages in map 0x20 enabled
> > >> cap 03[d0] = VPD
> > >> ecap 0001[100] = AER 1 0 fatal 0 non-fatal 2 corrected
> > >> ecap 0002[140] = VC 1 max VC0
> > >> ecap 0003[160] = Serial 1 01000000684ce000
> > >>
> > >> re0: flags=8843<UP,BROADCAST,RUNNING,SIMPLEX,MULTICAST> metric 0 mtu 1500
> > >> description: ToISP
> > >> options=8218b<RXCSUM,TXCSUM,VLAN_MTU,VLAN_HWCSUM,TSO4,WOL_MAGIC,LINKSTATE>
> > >> ether 00:21:85:1c:24:fa
> > >> media: Ethernet autoselect (100baseTX <full-duplex>)
> > >> status: active
> > >
> > > [...]
> > >
> > >> One is that re0 doesn't neogatiate direct link with a connected PC
> > >> (using non-crossover UTP), but sk0 does that easy. It seems to me that
> > >> according to RTL8111 chip specification there shouldn't be any
> > >> problem, probably it's a driver problem?
> > >>
> > >
> > > What is your link parter for re0? I don't remember whether the PHY
> > > hardware really supports automatic MDI crossover detection. Even if
> > > the PHY hardware does not support it, the link partner would be
> > > able to do that.
> > >
> > > And could you show me the output of dmesg(re(4) and rgephy(4) only)
> > > and "devinfo -rv | grep rgephy"?
> >
> > Here's info:
> >
> > re0: <RealTek 8168/8111 B/C/CP/D/DP/E/F PCIe Gigabit Ethernet> port
> > 0xd800-0xd8ff mem 0xfeaff000-0xfeafffff,0xf8ff0000-0xf8ffffff irq 17
> > at device 0.0 on pci4
> > re0: Using 1 MSI-X message
> > re0: Chip rev. 0x3c000000
> > re0: MAC rev. 0x00400000
> > miibus0: <MII bus> on re0
> > rgephy0: <RTL8169S/8110S/8211 1000BASE-T media interface> PHY 1 on miibus0
> > rgephy0: none, 10baseT, 10baseT-FDX, 10baseT-FDX-flow, 100baseTX,
> > 100baseTX-FDX, 100baseTX-FDX-flow, 1000baseT, 1000baseT-master,
> > 1000baseT-FDX, 1000baseT-FDX-master, 1000baseT-FDX-flow,
> > 1000baseT-FDX-flow-master, auto, auto-flow
> > re0: Ethernet address: 00:21:85:1c:24:fa
> >
> > devinfo -rv | grep rgephy
> > rgephy0 pnpinfo oui=0xe04c model=0x11 rev=0x2 at phyno=1
> >
> > This link connected to Realtek 8111E under Win7.
> > I'll repeat that when it's connected to sk0, everything works. Of
>
> e1000phy(4) supports automatic crossover detection/correction. I
> thought newer RealTek 8211 PHYs also support the feature but it
> seems it's not enabled by default. Could you try attached patch and
> let me know how it goes?
>
Attached patch.
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Index: sys/dev/mii/rgephy.c
===================================================================
--- sys/dev/mii/rgephy.c (revision 248449)
+++ sys/dev/mii/rgephy.c (working copy)
@@ -488,7 +488,7 @@ rgephy_load_dspcode(struct mii_softc *sc)
static void
rgephy_reset(struct mii_softc *sc)
{
- uint16_t ssr;
+ uint16_t pcr, ssr;
if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev == 3) {
/* RTL8211C(L) */
@@ -499,6 +499,15 @@ rgephy_reset(struct mii_softc *sc)
}
}
+ if (sc->mii_mpd_rev >= 2) {
+ pcr = PHY_READ(sc, RGEPHY_MII_PCR);
+ if ((pcr & RGEPHY_PCR_MDIX_AUTO) == 0) {
+ pcr &= ~RGEPHY_PCR_MDI_MASK;
+ pcr |= RGEPHY_PCR_MDIX_AUTO;
+ PHY_WRITE(sc, RGEPHY_MII_PCR, pcr);
+ }
+ }
+
mii_phy_reset(sc);
DELAY(1000);
rgephy_load_dspcode(sc);
Index: sys/dev/mii/rgephyreg.h
===================================================================
--- sys/dev/mii/rgephyreg.h (revision 248449)
+++ sys/dev/mii/rgephyreg.h (working copy)
@@ -137,6 +137,16 @@
#define RGEPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
#define RGEPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
+#define RGEPHY_MII_PCR 0x10 /* PHY Specific control register */
+#define RGEPHY_PCR_ASSERT_CRS 0x0800
+#define RGEPHY_PCR_FORCE_LINK 0x0400
+#define RGEPHY_PCR_MDI_MASK 0x0060
+#define RGEPHY_PCR_MDIX_AUTO 0x0040
+#define RGEPHY_PCR_MDIX_MANUAL 0x0020
+#define RGEPHY_PCR_MDI_MANUAL 0x0000
+#define RGEPHY_PCR_CLK125_DIS 0x0010
+#define RGEPHY_PCR_JABBER_DIS 0x0001
+
/* RTL8211B(L)/RTL8211C(L) */
#define RGEPHY_MII_SSR 0x11 /* PHY Specific status register */
#define RGEPHY_SSR_S1000 0x8000 /* 1000Mbps */
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