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Date:      Sun, 18 Sep 2016 21:28:09 +0000 (UTC)
From:      "Landon J. Fuller" <landonf@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r305953 - in head/sys: dev/bhnd mips/broadcom
Message-ID:  <201609182128.u8ILS9dl011620@repo.freebsd.org>

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Author: landonf
Date: Sun Sep 18 21:28:09 2016
New Revision: 305953
URL: https://svnweb.freebsd.org/changeset/base/305953

Log:
  Split bcm_mipscore.c into bcm_bmips (BMIPS32/BMIPS3300) and bcm_mips74k
  drivers.
  
  The BMIPS32/BMIPS3300 cores use a register layout distinct from the MIPS74K
  core, and are only found on siba(4) devices.
  
  Reviewed by:	mizhka
  Approved by:	adrian (mentor)
  Differential Revision:	https://reviews.freebsd.org/D7791

Added:
  head/sys/mips/broadcom/bcm_bmips.c   (contents, props changed)
  head/sys/mips/broadcom/bcm_bmips_exts.h
     - copied, changed from r305952, head/sys/mips/broadcom/bcm_mips_exts.h
  head/sys/mips/broadcom/bcm_bmipsreg.h   (contents, props changed)
  head/sys/mips/broadcom/bcm_mips74k.c
     - copied, changed from r305952, head/sys/mips/broadcom/bcm_mipscore.c
  head/sys/mips/broadcom/bcm_mips74kreg.h
     - copied, changed from r305952, head/sys/mips/broadcom/bcm_mipscore.h
Deleted:
  head/sys/mips/broadcom/bcm_mips_exts.h
  head/sys/mips/broadcom/bcm_mipscore.c
  head/sys/mips/broadcom/bcm_mipscore.h
Modified:
  head/sys/dev/bhnd/bhnd_subr.c
  head/sys/mips/broadcom/bcm_machdep.c
  head/sys/mips/broadcom/files.broadcom

Modified: head/sys/dev/bhnd/bhnd_subr.c
==============================================================================
--- head/sys/dev/bhnd/bhnd_subr.c	Sun Sep 18 20:47:55 2016	(r305952)
+++ head/sys/dev/bhnd/bhnd_subr.c	Sun Sep 18 21:28:09 2016	(r305953)
@@ -68,7 +68,7 @@ static const struct bhnd_core_desc {
 	BHND_CDESC(BCM, SRAM,		RAM,		"SRAM"),
 	BHND_CDESC(BCM, SDRAM,		RAM,		"SDRAM"),
 	BHND_CDESC(BCM, PCI,		PCI,		"PCI Bridge"),
-	BHND_CDESC(BCM, MIPS,		CPU,		"MIPS Core"),
+	BHND_CDESC(BCM, MIPS,		CPU,		"BMIPS CPU"),
 	BHND_CDESC(BCM, ENET,		ENET_MAC,	"Fast Ethernet MAC"),
 	BHND_CDESC(BCM, CODEC,		OTHER,		"V.90 Modem Codec"),
 	BHND_CDESC(BCM, USB,		USB_DUAL,	"USB 1.1 Device/Host Controller"),
@@ -85,7 +85,7 @@ static const struct bhnd_core_desc {
 	BHND_CDESC(BCM, APHY,		WLAN_PHY,	"802.11a PHY"),
 	BHND_CDESC(BCM, BPHY,		WLAN_PHY,	"802.11b PHY"),
 	BHND_CDESC(BCM, GPHY,		WLAN_PHY,	"802.11g PHY"),
-	BHND_CDESC(BCM, MIPS33,		CPU,		"MIPS3302 Core"),
+	BHND_CDESC(BCM, MIPS33,		CPU,		"BMIPS33 CPU"),
 	BHND_CDESC(BCM, USB11H,		USB_HOST,	"USB 1.1 Host Controller"),
 	BHND_CDESC(BCM, USB11D,		USB_DEV,	"USB 1.1 Device Controller"),
 	BHND_CDESC(BCM, USB20H,		USB_HOST,	"USB 2.0 Host Controller"),

Added: head/sys/mips/broadcom/bcm_bmips.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ head/sys/mips/broadcom/bcm_bmips.c	Sun Sep 18 21:28:09 2016	(r305953)
@@ -0,0 +1,123 @@
+/*-
+ * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ *    redistribution must be conditioned upon including a substantially
+ *    similar Disclaimer requirement for further binary redistribution.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/module.h>
+
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+
+#include <dev/bhnd/bhnd.h>
+
+#include "bcm_bmipsreg.h"
+
+/*
+ * BMIPS32 and BMIPS3300 core driver.
+ *
+ * These cores are only found on siba(4) chipsets, allowing
+ * us to assume the availability of siba interrupt registers.
+ */
+
+static const struct bhnd_device bcm_bmips_devs[] = {
+	BHND_DEVICE(BCM, MIPS33, NULL, NULL, BHND_DF_SOC),
+	BHND_DEVICE_END
+};
+
+struct bcm_bmips_softc {
+	device_t		 dev;
+	struct resource		*mem_res;
+	int			 mem_rid;
+};
+
+static int
+bcm_bmips_probe(device_t dev)
+{
+	const struct bhnd_device	*id;
+
+	id = bhnd_device_lookup(dev, bcm_bmips_devs,
+	    sizeof(bcm_bmips_devs[0]));
+	if (id == NULL)
+		return (ENXIO);
+
+	bhnd_set_default_core_desc(dev);
+	return (BUS_PROBE_DEFAULT);
+}
+
+static int
+bcm_bmips_attach(device_t dev)
+{
+	struct bcm_bmips_softc *sc;
+
+	sc = device_get_softc(dev);
+	sc->dev = dev;
+
+	/* Allocate bus resources */
+	sc->mem_rid = 0;
+	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
+	    RF_ACTIVE);
+	if (sc->mem_res == NULL)
+		return (ENXIO);
+
+	return (0);
+}
+
+static int
+bcm_bmips_detach(device_t dev)
+{
+	struct bcm_bmips_softc *sc;
+
+	sc = device_get_softc(dev);
+
+	bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res);
+
+	return (0);
+}
+
+static device_method_t bcm_bmips_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,			bcm_bmips_probe),
+	DEVMETHOD(device_attach,		bcm_bmips_attach),
+	DEVMETHOD(device_detach,		bcm_bmips_detach),
+	
+	DEVMETHOD_END
+};
+
+static devclass_t bcm_mips_devclass;
+
+DEFINE_CLASS_0(bcm_mips, bcm_bmips_driver, bcm_bmips_methods, sizeof(struct bcm_bmips_softc));
+EARLY_DRIVER_MODULE(bcm_bmips, bhnd, bcm_bmips_driver, bcm_mips_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY);
+
+MODULE_VERSION(bcm_bmips, 1);
+MODULE_DEPEND(bcm_bmips, bhnd, 1, 1, 1);

Copied and modified: head/sys/mips/broadcom/bcm_bmips_exts.h (from r305952, head/sys/mips/broadcom/bcm_mips_exts.h)
==============================================================================
--- head/sys/mips/broadcom/bcm_mips_exts.h	Sun Sep 18 20:47:55 2016	(r305952, copy source)
+++ head/sys/mips/broadcom/bcm_bmips_exts.h	Sun Sep 18 21:28:09 2016	(r305953)
@@ -52,8 +52,8 @@
     *
     *********************************************************************/
 
-#ifndef _MIPS_BROADCOM_BCM_MIPS_EXTS_H_
-#define _MIPS_BROADCOM_BCM_MIPS_EXTS_H_
+#ifndef _MIPS_BROADCOM_BCM_BMIPS_EXTS_H_
+#define _MIPS_BROADCOM_BCM_BMIPS_EXTS_H_
 
 #include <machine/cpufunc.h>
 
@@ -62,15 +62,15 @@
  * BMIPS330x MIPS32 core.
  */
 
-#define	MIPS_COP_0_BCMCFG	22
+#define	BMIPS_COP_0_BCMCFG	22
 
 /*
  * Custom CP0 Accessors
  */
 
-#define	BCM_MIPS_RW32_COP0_SEL(n,r,s)				\
+#define	BCM_BMIPS_RW32_COP0_SEL(n,r,s)				\
 static __inline uint32_t					\
-bcm_mips_rd_ ## n(void)						\
+bcm_bmips_rd_ ## n(void)					\
 {								\
 	int v0;							\
 	__asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";"	\
@@ -79,7 +79,7 @@ bcm_mips_rd_ ## n(void)						\
 	return (v0);						\
 }								\
 static __inline void						\
-bcm_mips_wr_ ## n(uint32_t a0)					\
+bcm_bmips_wr_ ## n(uint32_t a0)					\
 {								\
 	__asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";"	\
 			 __XSTRING(COP0_SYNC)";"		\
@@ -90,101 +90,101 @@ bcm_mips_wr_ ## n(uint32_t a0)					\
 	mips_barrier();						\
 } struct __hack
 
-BCM_MIPS_RW32_COP0_SEL(pllcfg1,	MIPS_COP_0_CONFIG,	1);
-BCM_MIPS_RW32_COP0_SEL(pllcfg2,	MIPS_COP_0_CONFIG,	2);
-BCM_MIPS_RW32_COP0_SEL(clksync,	MIPS_COP_0_CONFIG,	3);
-BCM_MIPS_RW32_COP0_SEL(pllcfg3,	MIPS_COP_0_CONFIG,	4);
-BCM_MIPS_RW32_COP0_SEL(rstcfg,	MIPS_COP_0_CONFIG,	5);
+BCM_BMIPS_RW32_COP0_SEL(pllcfg1,	MIPS_COP_0_CONFIG,	1);
+BCM_BMIPS_RW32_COP0_SEL(pllcfg2,	MIPS_COP_0_CONFIG,	2);
+BCM_BMIPS_RW32_COP0_SEL(clksync,	MIPS_COP_0_CONFIG,	3);
+BCM_BMIPS_RW32_COP0_SEL(pllcfg3,	MIPS_COP_0_CONFIG,	4);
+BCM_BMIPS_RW32_COP0_SEL(rstcfg,		MIPS_COP_0_CONFIG,	5);
 
 /*
  * Broadcom PLLConfig1 Register (22, select 1)
  */
 
 /* SoftMIPSPLLCfg */
-#define	MIPS_BCMCFG_PLLCFG1_MC_SHIFT	10
-#define	MIPS_BCMCFG_PLLCFG1_MC_MASK	0xFFFFFC00
+#define	BMIPS_BCMCFG_PLLCFG1_MC_SHIFT	10
+#define	BMIPS_BCMCFG_PLLCFG1_MC_MASK	0xFFFFFC00
 
 /* SoftISBPLLCfg */
-#define	MIPS_BCMCFG_PLLCFG1_BC_SHIFT	5
-#define	MIPS_BCMCFG_PLLCFG1_BC_MASK	0x000003E0
+#define	BMIPS_BCMCFG_PLLCFG1_BC_SHIFT	5
+#define	BMIPS_BCMCFG_PLLCFG1_BC_MASK	0x000003E0
 
 /* SoftRefPLLCfg */
-#define	MIPS_BCMCFG_PLLCFG1_PC_SHIFT	0
-#define	MIPS_BCMCFG_PLLCFG1_PC_MASK	0x0000001F
+#define	BMIPS_BCMCFG_PLLCFG1_PC_SHIFT	0
+#define	BMIPS_BCMCFG_PLLCFG1_PC_MASK	0x0000001F
 
 /*
  * Broadcom PLLConfig2 Register (22, select 2)
  */
 
 /* Soft1to1ClkRatio */
-#define	MIPS_BCMCFG_PLLCFG2_CR		(1<<23)
+#define	BMIPS_BCMCFG_PLLCFG2_CR		(1<<23)
 
 /* SoftUSBxPLLCfg */
-#define	MIPS_BCMCFG_PLLCFG2_UC_SHIFT	15
-#define	MIPS_BCMCFG_PLLCFG2_UC_MASK	0x007F8000
+#define	BMIPS_BCMCFG_PLLCFG2_UC_SHIFT	15
+#define	BMIPS_BCMCFG_PLLCFG2_UC_MASK	0x007F8000
 
 /* SoftIDExPLLCfg */
-#define	MIPS_BCMCFG_PLLCFG2_IC_SHIFT	7
-#define	MIPS_BCMCFG_PLLCFG2_IC_MASK	0x00007F80
+#define	BMIPS_BCMCFG_PLLCFG2_IC_SHIFT	7
+#define	BMIPS_BCMCFG_PLLCFG2_IC_MASK	0x00007F80
 
-#define	MIPS_BCMCFG_PLLCFG2_BE		(1<<6)	/* ISBxSoftCfgEnable */
-#define	MIPS_BCMCFG_PLLCFG2_UE		(1<<5)	/* USBxSoftCfgEnable */
-#define	MIPS_BCMCFG_PLLCFG2_IE		(1<<4)	/* IDExSoftCfgEnable */
-#define	MIPS_BCMCFG_PLLCFG2_CA		(1<<3)	/* CfgActive */
-#define	MIPS_BCMCFG_PLLCFG2_CF		(1<<2)	/* RefSoftCfgEnable */
-#define	MIPS_BCMCFG_PLLCFG2_CI		(1<<1)	/* ISBSoftCfgEnable */
-#define	MIPS_BCMCFG_PLLCFG2_CC		(1<<0)	/* MIPSSoftCfgEnable */
+#define	BMIPS_BCMCFG_PLLCFG2_BE		(1<<6)	/* ISBxSoftCfgEnable */
+#define	BMIPS_BCMCFG_PLLCFG2_UE		(1<<5)	/* USBxSoftCfgEnable */
+#define	BMIPS_BCMCFG_PLLCFG2_IE		(1<<4)	/* IDExSoftCfgEnable */
+#define	BMIPS_BCMCFG_PLLCFG2_CA		(1<<3)	/* CfgActive */
+#define	BMIPS_BCMCFG_PLLCFG2_CF		(1<<2)	/* RefSoftCfgEnable */
+#define	BMIPS_BCMCFG_PLLCFG2_CI		(1<<1)	/* ISBSoftCfgEnable */
+#define	BMIPS_BCMCFG_PLLCFG2_CC		(1<<0)	/* MIPSSoftCfgEnable */
 
 /*
  * Broadcom ClkSync Register (22, select 3)
  */
 /* SoftClkCfgHigh */
-#define	MIPS_BCMCFG_CLKSYNC_CH_SHIFT	16
-#define	MIPS_BCMCFG_CLKSYNC_CH_MASK	0xFFFF0000
+#define	BMIPS_BCMCFG_CLKSYNC_CH_SHIFT	16
+#define	BMIPS_BCMCFG_CLKSYNC_CH_MASK	0xFFFF0000
 
 /* SoftClkCfgLow */
-#define	MIPS_BCMCFG_CLKSYNC_CL_SHIFT	0
-#define	MIPS_BCMCFG_CLKSYNC_CL_MASK	0x0000FFFF
+#define	BMIPS_BCMCFG_CLKSYNC_CL_SHIFT	0
+#define	BMIPS_BCMCFG_CLKSYNC_CL_MASK	0x0000FFFF
 
 /*
  * Broadcom ISBxPLLConfig3 Register (22, select 4)
  */
 
 /* AsyncClkRatio */
-#define	MIPS_BCMCFG_PLLCFG3_AR_SHIFT	23
-#define	MIPS_BCMCFG_PLLCFG3_AR_MASK	0x01800000
+#define	BMIPS_BCMCFG_PLLCFG3_AR_SHIFT	23
+#define	BMIPS_BCMCFG_PLLCFG3_AR_MASK	0x01800000
 
-#define	MIPS_BCMCFG_PLLCFG3_SM		(1<<22)	/* SyncMode */
+#define	BMIPS_BCMCFG_PLLCFG3_SM		(1<<22)	/* SyncMode */
 
 /* SoftISBxPLLCfg */
-#define	MIPS_BCMCFG_PLLCFG3_IC_SHIFT	0
-#define	MIPS_BCMCFG_PLLCFG3_IC_MASK	0x003FFFFF
+#define	BMIPS_BCMCFG_PLLCFG3_IC_SHIFT	0
+#define	BMIPS_BCMCFG_PLLCFG3_IC_MASK	0x003FFFFF
 
 /*
  * Broadcom BRCMRstConfig Register (22, select 5)
  */
 
-#define	MIPS_BCMCFG_RSTCFG_SR		(1<<18)	/* SSMR */
-#define	MIPS_BCMCFG_RSTCFG_DT		(1<<16)	/* BHTD */
+#define	BMIPS_BCMCFG_RSTCFG_SR		(1<<18)	/* SSMR */
+#define	BMIPS_BCMCFG_RSTCFG_DT		(1<<16)	/* BHTD */
 
 /* RStSt */
-#define	MIPS_BCMCFG_RSTCFG_RS_SHIFT	8
-#define	MIPS_BCMCFG_RSTCFG_RS_MASK	0x00001F00
-#define	  MIPS_BCMCFG_RST_OTHER		0x00
-#define	  MIPS_BCMCFG_RST_SH		0x01
-#define	  MIPS_BCMCFG_RST_SS		0x02
-#define	  MIPS_BCMCFG_RST_EJTAG		0x04
-#define	  MIPS_BCMCFG_RST_WDOG		0x08
-#define	  MIPS_BCMCFG_RST_CRC		0x10
+#define	BMIPS_BCMCFG_RSTCFG_RS_SHIFT	8
+#define	BMIPS_BCMCFG_RSTCFG_RS_MASK	0x00001F00
+#define	  BMIPS_BCMCFG_RST_OTHER	0x00
+#define	  BMIPS_BCMCFG_RST_SH		0x01
+#define	  BMIPS_BCMCFG_RST_SS		0x02
+#define	  BMIPS_BCMCFG_RST_EJTAG	0x04
+#define	  BMIPS_BCMCFG_RST_WDOG		0x08
+#define	  BMIPS_BCMCFG_RST_CRC		0x10
 
-#define	MIPS_BCMCFG_RSTCFG_CR		(1<<7)	/* RStCr */
+#define	BMIPS_BCMCFG_RSTCFG_CR		(1<<7)	/* RStCr */
 
 /* WBMD */
-#define	MIPS_BCMCFG_RSTCFG_WD_SHIFT	3
-#define	MIPS_BCMCFG_RSTCFG_WD_MASK	0x00000078
+#define	BMIPS_BCMCFG_RSTCFG_WD_SHIFT	3
+#define	BMIPS_BCMCFG_RSTCFG_WD_MASK	0x00000078
 
-#define	MIPS_BCMCFG_RSTCFG_SS		(1<<2)	/* SSR */
-#define	MIPS_BCMCFG_RSTCFG_SH		(1<<1)	/* SHR */
-#define	MIPS_BCMCFG_RSTCFG_BR		(1<<0)	/* BdR */
+#define	BMIPS_BCMCFG_RSTCFG_SS		(1<<2)	/* SSR */
+#define	BMIPS_BCMCFG_RSTCFG_SH		(1<<1)	/* SHR */
+#define	BMIPS_BCMCFG_RSTCFG_BR		(1<<0)	/* BdR */
 
-#endif /* _MIPS_BROADCOM_BCM_MIPS_EXTS_H_ */
+#endif /* _MIPS_BROADCOM_BCM_BMIPS_EXTS_H_ */

Added: head/sys/mips/broadcom/bcm_bmipsreg.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ head/sys/mips/broadcom/bcm_bmipsreg.h	Sun Sep 18 21:28:09 2016	(r305953)
@@ -0,0 +1,73 @@
+/*-
+ * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ *    redistribution must be conditioned upon including a substantially
+ *    similar Disclaimer requirement for further binary redistribution.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ * 
+ * $FreeBSD$
+ */
+
+#ifndef	_MIPS_BROADCOM_BMIPSREG_H_
+#define	_MIPS_BROADCOM_BMIPSREG_H_
+
+/*
+ * Common BMIPS32/BMIPS3300 Registers
+ */
+#define	BCM_BMIPS_CORECTL		0x00	/**< core control */
+#define	  BCM_BMIPS_CORECTL_FORCE_RST	0x01	/**< force reset */
+#define	  BCM_BMIPS_CORECTL_NO_FLSH_EXC	0x02	/**< flash exception disable */
+#define	BCM_BMIPS_INTR_STATUS		0x20	/**< interrupt status */
+#define	BCM_BMIPS_INTR_MASK		0x24	/**< interrupt mask */
+#define	  BCM_BMIPS_TIMER_INTMASK	0x01	/**< timer interrupt mask */
+#define	BCM_BMIPS_TIMER_CTRL		0x28	/**< timer interval (?) */
+
+/*
+ * Broadcom BMIPS32 (BHND_COREID_MIPS)
+ */
+
+#define	BCM_BMIPS32_CORECTL		BCM_BMIPS_CORECTL
+#define	BCM_BMIPS32_BIST_STATUS		0x04	/**< built-in self-test status */
+#define	BCM_BMIPS32_INTR_STATUS		BCM_BMIPS_INTR_STATUS
+#define	BCM_BMIPS32_INTR_MASK		BCM_BMIPS_INTR_MASK
+#define	BCM_BMIPS32_TIMER_CTRL		BCM_BMIPS_TIMER_CTRL
+
+/*
+ * Broadcom BMIPS3300+ (BHND_COREID_MIPS33)
+ */
+
+#define	BCM_BMIPS33_CORECTL		BCM_BMIPS_CORECTL
+#define	BCM_BMIPS33_BIST_CTRL		0x04	/**< build-in self-test control */
+#define	  BCM_BMIPS33_BIST_CTRL_DUMP	0x01	/**< BIST dump */
+#define	  BCM_BMIPS33_BIST_CTRL_DEBUG	0x02	/**< BIST debug */
+#define	  BCM_BMIPS33_BIST_CTRL_HOLD	0x04	/**< BIST hold */
+#define	BCM_BMIPS33_BIST_STATUS		0x08	/**< built-in self-test status */
+#define	BCM_BMIPS33_INTR_STATUS		BCM_BMIPS_INTR_STATUS
+#define	BCM_BMIPS33_INTR_MASK		BCM_BMIPS_INTR_MASK
+#define	BCM_BMIPS33_TIMER_CTRL		BCM_BMIPS_TIMER_CTRL
+#define	BCM_BMIPS33_TEST_MUX_SEL	0x30	/**< test multiplexer select (?) */
+#define	BCM_BMIPS33_TEST_MUX_EN		0x34	/**< test multiplexer enable (?) */
+#define	BCM_BMIPS33_EJTAG_GPIO_EN	0x2C	/**< ejtag gpio enable */
+
+#endif /* _MIPS_BROADCOM_BMIPSREG_H_ */

Modified: head/sys/mips/broadcom/bcm_machdep.c
==============================================================================
--- head/sys/mips/broadcom/bcm_machdep.c	Sun Sep 18 20:47:55 2016	(r305952)
+++ head/sys/mips/broadcom/bcm_machdep.c	Sun Sep 18 21:28:09 2016	(r305953)
@@ -84,7 +84,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/bhnd/cores/pmu/bhnd_pmureg.h>
 
 #include "bcm_machdep.h"
-#include "bcm_mips_exts.h"
+#include "bcm_bmips_exts.h"
 
 #ifdef CFE
 #include <dev/cfe/cfe_api.h>
@@ -436,7 +436,7 @@ platform_reset(void)
 		bcm4785war = true;
 
 		/* Switch to async mode */
-		bcm_mips_wr_pllcfg3(MIPS_BCMCFG_PLLCFG3_SM);
+		bcm_bmips_wr_pllcfg3(BMIPS_BCMCFG_PLLCFG3_SM);
 	}
 
 	/* Set watchdog (PMU or ChipCommon) */

Copied and modified: head/sys/mips/broadcom/bcm_mips74k.c (from r305952, head/sys/mips/broadcom/bcm_mipscore.c)
==============================================================================
--- head/sys/mips/broadcom/bcm_mipscore.c	Sun Sep 18 20:47:55 2016	(r305952, copy source)
+++ head/sys/mips/broadcom/bcm_mips74k.c	Sun Sep 18 21:28:09 2016	(r305953)
@@ -1,5 +1,6 @@
 /*-
  * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com>
+ * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -34,41 +35,40 @@ __FBSDID("$FreeBSD$");
 #include <sys/kernel.h>
 #include <sys/bus.h>
 #include <sys/module.h>
-#include <sys/systm.h>
-#include <sys/errno.h>
-#include <sys/rman.h>
-#include <sys/stddef.h>
 
 #include <machine/bus.h>
+#include <sys/rman.h>
 #include <machine/resource.h>
 
 #include <dev/bhnd/bhnd.h>
-#include <dev/bhnd/bhndvar.h>
-#include <dev/bhnd/bhnd_ids.h>
 
-#include "bcm_mipscore.h"
+#include "bcm_mips74kreg.h"
 
-static const struct resource_spec mipscore_rspec[MIPSCORE_MAX_RSPEC] = {
-	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
-	{ -1, -1, 0 }
-};
-
-#define	MIPSCORE_DEV(_vendor, _core)	\
-	BHND_DEVICE(_vendor, _core, NULL, NULL, BHND_DF_SOC)
+/*
+ * Broadcom MIPS74K Core
+ *
+ * These cores are only found on bcma(4) chipsets, allowing
+ * us to assume the availability of bcma interrupt registers.
+ */
 
-struct bhnd_device mipscore_match[] = {
-	MIPSCORE_DEV(BCM, MIPS),
-	MIPSCORE_DEV(BCM, MIPS33),
-	MIPSCORE_DEV(MIPS, MIPS74K),
+static const struct bhnd_device bcm_mips74k_devs[] = {
+	BHND_DEVICE(MIPS, MIPS74K, NULL, NULL, BHND_DF_SOC),
 	BHND_DEVICE_END
 };
 
+struct bcm_mips74k_softc {
+	device_t		 dev;
+	struct resource		*mem_res;
+	int			 mem_rid;
+};
+
 static int
-mipscore_probe(device_t dev)
+bcm_mips74k_probe(device_t dev)
 {
-	const struct bhnd_device *id;
+	const struct bhnd_device	*id;
 
-	id = bhnd_device_lookup(dev, mipscore_match, sizeof(mipscore_match[0]));
+	id = bhnd_device_lookup(dev, bcm_mips74k_devs,
+	    sizeof(bcm_mips74k_devs[0]));
 	if (id == NULL)
 		return (ENXIO);
 
@@ -77,50 +77,51 @@ mipscore_probe(device_t dev)
 }
 
 static int
-mipscore_attach(device_t dev)
+bcm_mips74k_attach(device_t dev)
 {
-	struct mipscore_softc 	*sc;
-	struct resource 	*res;
-	uint32_t		 intmask;
-	uint16_t		 devid;
-	int			 error;
+	struct bcm_mips74k_softc *sc;
 
 	sc = device_get_softc(dev);
-	devid = bhnd_get_device(dev);
-
-	sc->devid = devid;
 	sc->dev = dev;
 
 	/* Allocate bus resources */
-	memcpy(sc->rspec, mipscore_rspec, sizeof(sc->rspec));
-	error = bhnd_alloc_resources(dev, sc->rspec, sc->res);
-	if (error)
-		return (error);
-
-	res = sc->res[0]->res;
-	if (res == NULL)
+	sc->mem_rid = 0;
+	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
+	    RF_ACTIVE);
+	if (sc->mem_res == NULL)
 		return (ENXIO);
 
-	if (devid == BHND_COREID_MIPS74K) {
-		intmask = (1 << 31);
-		/* Use intmask5 register to route the timer interrupt */
-		bus_write_4(res, offsetof(struct mipscore_regs, intmask[5]),
-				intmask);
-	}
+	/* Route MIPS timer to IRQ5 */
+	bus_write_4(sc->mem_res, BCM_MIPS74K_INTR5_SEL,
+	    (1<<BCM_MIPS74K_TIMER_IVEC));
+
+	return (0);
+}
+
+static int
+bcm_mips74k_detach(device_t dev)
+{
+	struct bcm_mips74k_softc	*sc;
+
+	sc = device_get_softc(dev);
+
+	bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res);
 
 	return (0);
 }
 
-static device_method_t mipscore_methods[] = {
-		DEVMETHOD(device_probe, 	mipscore_probe),
-		DEVMETHOD(device_attach,	mipscore_attach),
-		DEVMETHOD_END
+static device_method_t bcm_mips74k_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,			bcm_mips74k_probe),
+	DEVMETHOD(device_attach,		bcm_mips74k_attach),
+	DEVMETHOD(device_detach,		bcm_mips74k_detach),
+	
+	DEVMETHOD_END
 };
 
-devclass_t bhnd_mipscore_devclass;
+static devclass_t bcm_mips_devclass;
 
-DEFINE_CLASS_0(bhnd_mips, mipscore_driver, mipscore_methods,
-    sizeof(struct mipscore_softc));
-EARLY_DRIVER_MODULE(bhnd_mips, bhnd, mipscore_driver,
-    bhnd_mipscore_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY);
-MODULE_VERSION(bhnd_mips, 1);
+DEFINE_CLASS_0(bcm_mips, bcm_mips74k_driver, bcm_mips74k_methods, sizeof(struct bcm_mips74k_softc));
+EARLY_DRIVER_MODULE(bcm_mips74k, bhnd, bcm_mips74k_driver, bcm_mips_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY);
+MODULE_VERSION(bcm_mips74k, 1);
+MODULE_DEPEND(bcm_mips74k, bhnd, 1, 1, 1);

Copied and modified: head/sys/mips/broadcom/bcm_mips74kreg.h (from r305952, head/sys/mips/broadcom/bcm_mipscore.h)
==============================================================================
--- head/sys/mips/broadcom/bcm_mipscore.h	Sun Sep 18 20:47:55 2016	(r305952, copy source)
+++ head/sys/mips/broadcom/bcm_mips74kreg.h	Sun Sep 18 21:28:09 2016	(r305953)
@@ -1,5 +1,5 @@
 /*-
- * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com>
+ * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -25,36 +25,38 @@
  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGES.
- *
- *  $FreeBSD$
+ * 
+ * $FreeBSD$
  */
 
-#ifndef _BHND_CORES_MIPS_MIPSCOREVAR_H_
-#define _BHND_CORES_MIPS_MIPSCOREVAR_H_
+#ifndef	_MIPS_BROADCOM_MIPS74KREG_H_
+#define	_MIPS_BROADCOM_MIPS74KREG_H_
+
+#define	BCM_MIPS74K_CORECTL		0x00	/**< core control */
+#define	BCM_MIPS74K_EXCBASE		0x04	/**< exception base */
+
+#define	BCM_MIPS74K_BIST_STATUS		0x0C	/**< built-in self-test status */
+#define	BCM_MIPS74K_INTR_STATUS		0x10	/**< interrupt status */
+
+/* INTR(0-5)_MASK map bcma(4) OOB interrupt bus lines to MIPS hardware
+ * interrupts. */
+#define	BCM_MIPS74K_INTR0_SEL		0x14	/**< IRQ0 OOBSEL mask */
+#define	BCM_MIPS74K_INTR1_SEL		0x18	/**< IRQ1 OOBSEL mask */
+#define	BCM_MIPS74K_INTR2_SEL		0x1C	/**< IRQ2 OOBSEL mask */
+#define	BCM_MIPS74K_INTR3_SEL		0x20	/**< IRQ3 OOBSEL mask */
+#define	BCM_MIPS74K_INTR4_SEL		0x24	/**< IRQ4 OOBSEL mask */
+#define	BCM_MIPS74K_INTR5_SEL		0x28	/**< IRQ5 OOBSEL mask */
+
+#define	BCM_MIPS74K_INTR_SEL(_intr)	\
+	(BCM_MIPS74K_INTR0_SEL + ((_intr) * 4))
+
+#define	BCM_MIPS74K_NMI_MASK		0x2C	/**< nmi mask */
+
+#define	BCM_MIPS74K_GPIO_SEL		0x40	/**< gpio select */
+#define	BCM_MIPS74K_GPIO_OUT		0x44	/**< gpio output enable */
+#define	BCM_MIPS74K_GPIO_EN		0x48	/**< gpio enable */
 
-#define	MIPSCORE_MAX_RSPEC 2
 
-struct mipscore_softc {
-	device_t		dev;	/* CPU device */
-	uint32_t		devid;
-	struct resource_spec	rspec[MIPSCORE_MAX_RSPEC];
-	struct bhnd_resource	*res[MIPSCORE_MAX_RSPEC];
-};
-
-struct mipscore_regs {
-        uint32_t	corecontrol;
-        uint32_t	exceptionbase;
-        uint32_t	PAD1[1];	/* unmapped address */
-        uint32_t	biststatus;
-        uint32_t	intstatus;
-        uint32_t	intmask[6];
-        uint32_t	nmimask;
-        uint32_t	PAD2[4];	/* unmapped addresses */
-        uint32_t	gpioselect;
-        uint32_t	gpiooutput;
-        uint32_t	gpioenable;
-        uint32_t	PAD3[101];	/* unmapped addresses */
-        uint32_t	clkcontrolstatus;
-};
+#define	BCM_MIPS74K_TIMER_IVEC		31	/**< MIPS timer OOBSEL value */
 
-#endif /* _BHND_CORES_MIPS_MIPSCOREVAR_H_ */
+#endif /* _MIPS_BROADCOM_MIPS74KREG_H_ */

Modified: head/sys/mips/broadcom/files.broadcom
==============================================================================
--- head/sys/mips/broadcom/files.broadcom	Sun Sep 18 20:47:55 2016	(r305952)
+++ head/sys/mips/broadcom/files.broadcom	Sun Sep 18 21:28:09 2016	(r305953)
@@ -5,6 +5,8 @@
 # which are believed to be devices we have drivers for
 # which just need to be tweaked for attachment to an BHND system bus.
 mips/broadcom/bcm_machdep.c		standard
+mips/broadcom/bcm_bmips.c		optional siba_nexus siba
+mips/broadcom/bcm_mips74k.c		optional bcma_nexus bcma
 mips/broadcom/bcm_pmu.c			standard
 mips/mips/tick.c			standard
 mips/mips/mips_pic.c			standard
@@ -15,7 +17,6 @@ kern/msi_if.m				optional intrng
 
 mips/broadcom/uart_cpu_chipc.c		optional uart
 mips/broadcom/uart_bus_chipc.c		optional uart
-mips/broadcom/bcm_mipscore.c		standard
 
 # TODO: Replace with BCM47xx/57xx/etc-aware geom_map
 geom/geom_flashmap.c			standard
@@ -23,4 +24,4 @@ geom/geom_flashmap.c			standard
 # USB bits
 dev/bhnd/cores/usb/bhnd_usb.c		optional usb
 dev/bhnd/cores/usb/bhnd_ehci.c		optional ehci
-dev/bhnd/cores/usb/bhnd_ohci.c		optional ohci
\ No newline at end of file
+dev/bhnd/cores/usb/bhnd_ohci.c		optional ohci



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