Date: Fri, 15 Dec 2000 23:50:50 +0100 From: Bernd Walter <ticso@cicely5.cicely.de> To: John Baldwin <jhb@FreeBSD.org> Cc: freebsd-alpha@FreeBSD.org Subject: Re: mb and wmb in atomic_ Message-ID: <20001215235049.A62322@cicely5.cicely.de> In-Reply-To: <XFMail.001215131925.jhb@FreeBSD.org>; from jhb@FreeBSD.org on Fri, Dec 15, 2000 at 01:19:25PM -0800 References: <20001215211930.D62048@cicely5.cicely.de> <XFMail.001215131925.jhb@FreeBSD.org>
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On Fri, Dec 15, 2000 at 01:19:25PM -0800, John Baldwin wrote: > > On 15-Dec-00 Bernd Walter wrote: > > On Fri, Dec 15, 2000 at 11:35:47AM -0800, John Baldwin wrote: > >> > >> On 15-Dec-00 Bernd Walter wrote: > >> > Why are the mb and wmb operations needed in the atomic_ functions? > >> > If I understood it correctly the locked operations are in synced > >> > with others CPUs and there is no memory operation beside the variable > >> > itself. > >> > >> They should probably only be used with the 'acq' and 'rel' variants. Hmm, > >> btw, > >> it looks like I have the order of the barriers in the 'acq' and 'rel' > >> variants > >> wrong. The barriers should be on the inside, not the outside. Anyone > >> disagree? > > > > Depending on atomic(9) I agree. > > I don't asume the acq variant realy needs one as the locked operation > > should be finished at once at least out of the CPUs thus no post operation > > has the chance to make anything before. > > Do we have the situation anywhere that the bus reorders memory access? > > Do we care about this? > > Can the CPU perform out-of-order execution though? And out-of-order memory > accesses as a result? That is what memory barriers really protect you against. Mmmm - true. I silently asumed conditioned store operations aren't reordered but in fact I havn't found a definition for this. -- B.Walter COSMO-Project http://www.cosmo-project.de ticso@cicely.de Usergroup info@cosmo-project.de To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-alpha" in the body of the message
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