Date: Sat, 30 Mar 2002 15:27:40 -0800 (PST) From: Thomas Moestl <tmm@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 8690 for review Message-ID: <200203302327.g2UNReQ91440@freefall.freebsd.org>
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http://people.freebsd.org/~peter/p4db/chv.cgi?CH=8690 Change 8690 by tmm@tmm_sparc64 on 2002/03/30 15:27:24 Integ. from sparc64-tmm: fix crashes in the case of more than one 4M kernel page being used, adjust UPA_MEMSTART. Affected files ... ... //depot/projects/sparc64/sys/sparc64/include/tlb.h#33 integrate ... //depot/projects/sparc64/sys/sparc64/include/upa.h#7 integrate ... //depot/projects/sparc64/sys/sparc64/sparc64/pmap.c#81 integrate Differences ... ==== //depot/projects/sparc64/sys/sparc64/include/tlb.h#33 (text+ko) ==== @@ -29,11 +29,6 @@ #ifndef _MACHINE_TLB_H_ #define _MACHINE_TLB_H_ -#define TLB_SLOT_COUNT 64 /* XXX */ - -#define TLB_SLOT_TSB_KERNEL_MIN 62 /* XXX */ -#define TLB_SLOT_KERNEL 63 /* XXX */ - #define TLB_DAR_SLOT_SHIFT (3) #define TLB_DAR_SLOT(slot) ((slot) << TLB_DAR_SLOT_SHIFT) ==== //depot/projects/sparc64/sys/sparc64/include/upa.h#7 (text+ko) ==== @@ -28,7 +28,7 @@ #ifndef _MACHINE_UPA_H_ #define _MACHINE_UPA_H_ -#define UPA_MEMSTART 0x1fc00000000UL +#define UPA_MEMSTART 0x1c000000000UL #define UPA_MEMEND 0x1ffffffffffUL #define UPA_CR_MID_SHIFT (17) ==== //depot/projects/sparc64/sys/sparc64/sparc64/pmap.c#81 (text+ko) ==== @@ -147,12 +147,6 @@ vm_offset_t kernel_vm_end; /* - * The locked kernel page the kernel binary was loaded into. This will need - * to become a list later. - */ -vm_offset_t kernel_page; - -/* * Kernel pmap. */ struct pmap kernel_pmap_store; @@ -302,10 +296,6 @@ virtual_avail = roundup2(ekva, PAGE_SIZE_4M); virtual_end = VM_MAX_KERNEL_ADDRESS; - /* Look up the page the kernel binary was loaded into. */ - kernel_page = TD_GET_PA(ldxa(TLB_DAR_SLOT(TLB_SLOT_KERNEL), - ASI_DTLB_DATA_ACCESS_REG)); - /* * Find out what physical memory is available from the prom and * initialize the phys_avail array. This must be done before @@ -348,6 +338,17 @@ bzero(tsb_kernel, KVA_PAGES * PAGE_SIZE_4M); /* + * Enter fake 8k pages for the 4MB kernel pages, so that + * pmap_kextract() will work for them. + */ + for (i = 0; i < kernel_tlb_slots; i++) { + va = TV_GET_VA(kernel_ttes[i].tte_vpn); + pa = TD_GET_PA(kernel_ttes[i].tte_data); + for (off = 0; off < PAGE_SIZE_4M; off += PAGE_SIZE) + pmap_kenter(va + off, pa + off); + } + + /* * Allocate a kernel stack with guard page for thread0 and map it into * the kernel tsb. */ @@ -435,7 +436,6 @@ vm_offset_t va; vm_offset_t pa; u_long data; - u_int slot; u_long s; int i; @@ -444,15 +444,14 @@ /* * Map the 4mb tsb pages. */ - slot = TLB_SLOT_TSB_KERNEL_MIN; - for (i = 0; i < KVA_PAGES; i++, slot++) { + for (i = 0; i < KVA_PAGES; i++) { va = (vm_offset_t)tsb_kernel + i * PAGE_SIZE_4M; pa = tsb_kernel_phys + i * PAGE_SIZE_4M; data = TD_V | TD_4M | TD_PA(pa) | TD_L | TD_CP | TD_CV | TD_P | TD_W; stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(TLB_CTX_KERNEL)); - stxa(TLB_DAR_SLOT(slot), ASI_DTLB_DATA_ACCESS_REG, data); + stxa(0, ASI_DTLB_DATA_IN_REG, data); membar(Sync); } @@ -619,8 +618,6 @@ struct tte *tp; u_long d; - if (va >= KERNBASE && va < KERNBASE + PAGE_SIZE_4M) - return (kernel_page + (va & PAGE_MASK_4M)); tp = tsb_kvtotte(va); d = tp->tte_data; if ((d & TD_V) == 0) To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe p4-projects" in the body of the message
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