Date: Thu, 24 Apr 2014 00:27:34 +0000 (UTC) From: Peter Grehan <grehan@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r264846 - head/sys/amd64/vmm/intel Message-ID: <201404240027.s3O0RY0x023032@svn.freebsd.org>
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Author: grehan Date: Thu Apr 24 00:27:34 2014 New Revision: 264846 URL: http://svnweb.freebsd.org/changeset/base/264846 Log: Allow the guest to read the TSC via MSR 0x10. NetBSD/amd64 does this, as does Linux on AMD CPUs. Reviewed by: neel MFC after: 3 weeks Modified: head/sys/amd64/vmm/intel/vmx.c Modified: head/sys/amd64/vmm/intel/vmx.c ============================================================================== --- head/sys/amd64/vmm/intel/vmx.c Wed Apr 23 23:13:46 2014 (r264845) +++ head/sys/amd64/vmm/intel/vmx.c Thu Apr 24 00:27:34 2014 (r264846) @@ -863,6 +863,11 @@ vmx_vminit(struct vm *vm, pmap_t pmap) * MSR_EFER is saved and restored in the guest VMCS area on a * VM exit and entry respectively. It is also restored from the * host VMCS area on a VM exit. + * + * The TSC MSR is exposed read-only. Writes are disallowed as that + * will impact the host TSC. + * XXX Writes would be implemented with a wrmsr trap, and + * then modifying the TSC offset in the VMCS. */ if (guest_msr_rw(vmx, MSR_GSBASE) || guest_msr_rw(vmx, MSR_FSBASE) || @@ -870,7 +875,8 @@ vmx_vminit(struct vm *vm, pmap_t pmap) guest_msr_rw(vmx, MSR_SYSENTER_ESP_MSR) || guest_msr_rw(vmx, MSR_SYSENTER_EIP_MSR) || guest_msr_rw(vmx, MSR_KGSBASE) || - guest_msr_rw(vmx, MSR_EFER)) + guest_msr_rw(vmx, MSR_EFER) || + guest_msr_ro(vmx, MSR_TSC)) panic("vmx_vminit: error setting guest msr access"); /*
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