Date: Wed, 7 Jun 95 19:08:43 MDT From: terry@cs.weber.edu (Terry Lambert) To: rgrimes@gndrsh.aac.dev.com (Rodney W. Grimes) Cc: davidg@Root.COM, maddox@CS.Berkeley.EDU, sysseh@devetir.qld.gov.au, bugs@FreeBSD.org Subject: Re: 2.0.5-A: Very disheartening? Message-ID: <9506080108.AA11564@cs.weber.edu> In-Reply-To: <199506072023.NAA03182@gndrsh.aac.dev.com> from "Rodney W. Grimes" at Jun 7, 95 01:23:44 pm
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> > > I do know for certain that any write to memory of data that is in the > > > Pentium I cache will cause it to invalidate the I cache line. > > > > It will, according to "The Undocumented PC". > > I take it that you mean it will invalidate the prefetch buffer, I > already said I knew it would invalidate the I cache. Looks like > you got your reply to the wrong part of context. You're right. I meant instruction prefetch cache. As to the P6, I think it updates the prefetch as well: my basis for this is that LISP and Forth-like languages can have severe conniptions when the code they modified isn't modified by the time it runs, and this was the rationale I heard for the P5 fix. Terry Lambert terry@cs.weber.edu --- Any opinions in this posting are my own and not those of my present or previous employers.
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