Date: Thu, 23 Mar 1995 09:50:27 -0800 (PST) From: "Rodney W. Grimes" <rgrimes@gndrsh.aac.dev.com> To: jhs@regent.e-technik.tu-muenchen.de (Julian Howard Stacey) Cc: hardware@FreeBSD.org Subject: Re: 3-1-1-1 burst Message-ID: <199503231750.JAA01313@gndrsh.aac.dev.com> In-Reply-To: <199503212105.WAA08255@vector.eikon.e-technik.tu-muenchen.de> from "Julian Howard Stacey" at Mar 21, 95 10:05:53 pm
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> > > Re. > > and the bility of Poul to go to a 3-1-1-1 burst. > > Sorry guys, what does this mean ? some convention I'm missing ? This is a kinda Intel thing, but I have seen it used other places when talking about burst mode bus transfers A burst mode transfer is one where you provide a starting address and/or data on the first cycle, then data on subsequent cycles. Often the timing is different for these cycles, in the above the first number is how many clock ticks it takes for the setup of the address and the first data transfer. The other three numbers are the cycles for the 2nd, 3rd and 4th data word. This is for a 4 word burst which is what i[45]86 chips use for there burst mode. Due to pipeline design and other factors this can be things like 4-3-2-2, or even as slow as 7-4-4-4. When working with designs that have N word burst this is often written differently. > PS you may assume I at least once I knew hardware, (I designed my own > NSC 32016 board etc), but I never did know PC archania too well :-) > (though I suspect this is generic cache parlance here, not Intel PC specific ?) > > PS the original header line: > To: phk@ref.tfs.com rgrimes@gndrsh.aac.dev.com > Cc: core@freebsd.org hackers@freebsd.org nate@sneezy.sri.com > I have stripped to: > To: hardware@freebsd.org > > Julian S > -- Rod Grimes rgrimes@gndrsh.aac.dev.com Accurate Automation Company Custom computers for FreeBSD
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