Date: Tue, 19 Mar 2013 21:48:39 GMT From: svn-freebsd-gecko@chruetertee.ch To: freebsd-gecko@freebsd.org Subject: [SVN-Commit] r1216 - in trunk: devel/nspr www/firefox-nightly www/firefox-nightly/files Message-ID: <201303192148.r2JLmdq4020438@trillian.chruetertee.ch>
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Author: jbeich
Date: Tue Mar 19 21:48:38 2013
New Revision: 1216
Log:
update
Deleted:
trunk/www/firefox-nightly/files/patch-bug807883
Modified:
trunk/devel/nspr/Makefile
trunk/devel/nspr/distinfo
trunk/www/firefox-nightly/Makefile
trunk/www/firefox-nightly/Makefile.hgrev
trunk/www/firefox-nightly/distinfo
trunk/www/firefox-nightly/files/patch-bug851880
Modified: trunk/devel/nspr/Makefile
==============================================================================
--- trunk/devel/nspr/Makefile Sun Mar 17 22:05:15 2013 (r1215)
+++ trunk/devel/nspr/Makefile Tue Mar 19 21:48:38 2013 (r1216)
@@ -6,7 +6,7 @@
# $MCom: ports-experimental/devel/nspr/Makefile,v 1.6 2008/03/12 13:06:56 ahze Exp $
PORTNAME= nspr
-DISTVERSION= 4.9.5
+DISTVERSION= 4.9.6
CATEGORIES= devel
MASTER_SITES= MOZILLA
MASTER_SITE_SUBDIR= nspr/releases/v${PORTVERSION}/src
Modified: trunk/devel/nspr/distinfo
==============================================================================
--- trunk/devel/nspr/distinfo Sun Mar 17 22:05:15 2013 (r1215)
+++ trunk/devel/nspr/distinfo Tue Mar 19 21:48:38 2013 (r1216)
@@ -1,2 +1,2 @@
-SHA256 (nspr-4.9.5.tar.gz) = 616ab65c849155c9ed0e5f502530a241cc9108e278275aa448b417ae632c7604
-SIZE (nspr-4.9.5.tar.gz) = 1156396
+SHA256 (nspr-4.9.6.tar.gz) = 7693fddd3c5cc15d53a50df53ab5dcdaa2eb58f5003302690559471744d6c6f9
+SIZE (nspr-4.9.6.tar.gz) = 1163033
Modified: trunk/www/firefox-nightly/Makefile
==============================================================================
--- trunk/www/firefox-nightly/Makefile Sun Mar 17 22:05:15 2013 (r1215)
+++ trunk/www/firefox-nightly/Makefile Tue Mar 19 21:48:38 2013 (r1216)
@@ -13,7 +13,7 @@
MAINTAINER= gecko@FreeBSD.org
COMMENT= Web browser based on the browser portion of Mozilla
-BUILD_DEPENDS= nspr>=4.9.4:${PORTSDIR}/devel/nspr \
+BUILD_DEPENDS= nspr>=4.9.6:${PORTSDIR}/devel/nspr \
nss>=3.14.2:${PORTSDIR}/security/nss \
sqlite3>=3.7.14.1:${PORTSDIR}/databases/sqlite3 \
${PYTHON_PKGNAMEPREFIX}sqlite3>0:${PORTSDIR}/databases/py-sqlite3 \
Modified: trunk/www/firefox-nightly/Makefile.hgrev
==============================================================================
--- trunk/www/firefox-nightly/Makefile.hgrev Sun Mar 17 22:05:15 2013 (r1215)
+++ trunk/www/firefox-nightly/Makefile.hgrev Tue Mar 19 21:48:38 2013 (r1216)
@@ -1 +1 @@
-HGREV= 125126:09f72f45a0b7
+HGREV= 125380:f4394e306dad
Modified: trunk/www/firefox-nightly/distinfo
==============================================================================
--- trunk/www/firefox-nightly/distinfo Sun Mar 17 22:05:15 2013 (r1215)
+++ trunk/www/firefox-nightly/distinfo Tue Mar 19 21:48:38 2013 (r1216)
@@ -1,2 +1,2 @@
-SHA256 (firefox-nightly/09f72f45a0b7.tar.bz2) = 8fbcca20b7f3b98498514995cdf200426f22de5d0dec5ea3209eb47fede9148a
-SIZE (firefox-nightly/09f72f45a0b7.tar.bz2) = 109449607
+SHA256 (firefox-nightly/f4394e306dad.tar.bz2) = b5540a98c7f9b5036314c5a634091b889336de6ce5e69e1258215735dfb24b83
+SIZE (firefox-nightly/f4394e306dad.tar.bz2) = 109212098
Deleted: trunk/www/firefox-nightly/files/patch-bug807883
==============================================================================
--- trunk/www/firefox-nightly/files/patch-bug807883 Tue Mar 19 21:48:38 2013 (r1215)
+++ /dev/null 00:00:00 1970 (deleted)
@@ -1,109 +0,0 @@
-commit 9bc203a
-Author: Wan-Teh Chang <wtc@google.com>
-Date: Tue Feb 12 08:54:38 2013 -0800
-
- Bug 807883: Use the new PL_SizeOfArenaPoolExcludingPool function
- in NSPR 4.9.6. Portions of the patch were written by Nicholas
- Nethercote <n.nethercote@gmail.com>. r=n.nethercote.
----
- configure.in | 2 +-
- layout/base/nsPresArena.cpp | 11 ++---------
- modules/libpref/src/prefapi.cpp | 9 +--------
- xpcom/components/nsCategoryManager.cpp | 9 +--------
- xpcom/components/nsComponentManager.cpp | 9 +--------
- 5 files changed, 6 insertions(+), 34 deletions(-)
-
-diff --git configure.in configure.in
-index b2225f4..55e4cd1 100644
---- configure.in
-+++ configure.in
-@@ -3856,7 +3856,7 @@
- _USE_SYSTEM_NSPR=1 )
-
- if test -n "$_USE_SYSTEM_NSPR"; then
-- AM_PATH_NSPR(4.9.6, [MOZ_NATIVE_NSPR=1], [AC_MSG_ERROR([your don't have NSPR installed or your version is too old])])
-+ AM_PATH_NSPR(4.9.4, [MOZ_NATIVE_NSPR=1], [AC_MSG_ERROR([your don't have NSPR installed or your version is too old])])
- fi
-
- if test -n "$MOZ_NATIVE_NSPR"; then
-diff --git layout/base/nsPresArena.cpp layout/base/nsPresArena.cpp
-index 8721eec..7daafb4 100644
---- layout/base/nsPresArena.cpp
-+++ layout/base/nsPresArena.cpp
-@@ -405,7 +405,15 @@
- size_t SizeOfIncludingThisFromMalloc(nsMallocSizeOfFun aMallocSizeOf) const
- {
- size_t n = aMallocSizeOf(this);
-- n += PL_SizeOfArenaPoolExcludingPool(&mPool, aMallocSizeOf);
-+
-+ // The first PLArena is within the PLArenaPool, i.e. within |this|, so we
-+ // don't measure it. Subsequent PLArenas are by themselves and must be
-+ // measured.
-+ const PLArena *arena = mPool.first.next;
-+ while (arena) {
-+ n += aMallocSizeOf(arena);
-+ arena = arena->next;
-+ }
- n += mFreeLists.SizeOfExcludingThis(SizeOfFreeListEntryExcludingThis,
- aMallocSizeOf);
- return n;
-diff --git modules/libpref/src/prefapi.cpp modules/libpref/src/prefapi.cpp
-index 85dea39..0dd74de 100644
---- modules/libpref/src/prefapi.cpp
-+++ modules/libpref/src/prefapi.cpp
-@@ -809,7 +809,14 @@
- size_t
- pref_SizeOfPrivateData(nsMallocSizeOfFun aMallocSizeOf)
- {
-- size_t n = PL_SizeOfArenaPoolExcludingPool(&gPrefNameArena, aMallocSizeOf);
-+ size_t n = 0;
-+ // The first PLArena is within the PLArenaPool, so start measuring
-+ // malloc'd data with the second arena.
-+ const PLArena* arena = gPrefNameArena.first.next;
-+ while (arena) {
-+ n += aMallocSizeOf(arena);
-+ arena = arena->next;
-+ }
- for (struct CallbackNode* node = gCallbacks; node; node = node->next) {
- n += aMallocSizeOf(node);
- n += aMallocSizeOf(node->domain);
-diff --git xpcom/components/nsCategoryManager.cpp xpcom/components/nsCategoryManager.cpp
-index 8e964bb..62e873c 100644
---- xpcom/components/nsCategoryManager.cpp
-+++ xpcom/components/nsCategoryManager.cpp
-@@ -512,7 +512,14 @@
- {
- size_t n = aMallocSizeOf(this);
-
-- n += PL_SizeOfArenaPoolExcludingPool(&mArena, aMallocSizeOf);
-+ // The first PLArena is within the PLArenaPool, i.e. within |this|, so we
-+ // don't measure it. Subsequent PLArenas are by themselves and must be
-+ // measured.
-+ const PLArena *arena = mArena.first.next;
-+ while (arena) {
-+ n += aMallocSizeOf(arena);
-+ arena = arena->next;
-+ }
-
- n += mTable.SizeOfExcludingThis(SizeOfCategoryManagerTableEntryExcludingThis,
- aMallocSizeOf);
-diff --git xpcom/components/nsComponentManager.cpp xpcom/components/nsComponentManager.cpp
-index f6f9f0a..c80f4c3 100644
---- xpcom/components/nsComponentManager.cpp
-+++ xpcom/components/nsComponentManager.cpp
-@@ -1680,7 +1680,14 @@
- n += mKnownStaticModules.SizeOfExcludingThis(aMallocSizeOf);
- n += mKnownModules.SizeOfExcludingThis(nullptr, aMallocSizeOf);
-
-- n += PL_SizeOfArenaPoolExcludingPool(&mArena, aMallocSizeOf);
-+ // The first PLArena is within the PLArenaPool, i.e. within |this|, so we
-+ // don't measure it. Subsequent PLArenas are by themselves and must be
-+ // measured.
-+ const PLArena *arena = mArena.first.next;
-+ while (arena) {
-+ n += aMallocSizeOf(arena);
-+ arena = arena->next;
-+ }
-
- n += mPendingServices.SizeOfExcludingThis(aMallocSizeOf);
-
Modified: trunk/www/firefox-nightly/files/patch-bug851880
==============================================================================
--- trunk/www/firefox-nightly/files/patch-bug851880 Sun Mar 17 22:05:15 2013 (r1215)
+++ trunk/www/firefox-nightly/files/patch-bug851880 Tue Mar 19 21:48:38 2013 (r1216)
@@ -1,159 +1,441 @@
diff --git js/src/ion/AsmJS.h js/src/ion/AsmJS.h
-index 52f09fc..f806452 100644
+index 17f2bc8..1600131 100644
--- js/src/ion/AsmJS.h
+++ js/src/ion/AsmJS.h
-@@ -13,7 +13,7 @@
+@@ -11,9 +11,8 @@
+ // asm.js compilation is only available on desktop x86/x64 at the moment.
+ // Don't panic, mobile support is coming soon.
#if defined(JS_ION) && \
- !defined(ANDROID) && \
- (defined(JS_CPU_X86) || defined(JS_CPU_X64)) && \
-- (defined(__linux__) || defined(XP_WIN) || defined(XP_MACOSX))
-+ (defined(__linux__) || defined(__DragonFly__) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(XP_WIN) || defined(XP_MACOSX))
+- !defined(ANDROID) && \
+- (defined(JS_CPU_X86) || defined(JS_CPU_X64)) && \
+- (defined(__linux__) || defined(XP_WIN))
++ (!defined(ANDROID) && !defined(XP_MACOSX)) && \
++ (defined(JS_CPU_X86) || defined(JS_CPU_X64))
# define JS_ASMJS
#endif
diff --git js/src/ion/AsmJSSignalHandlers.cpp js/src/ion/AsmJSSignalHandlers.cpp
-index 45eeac9..d4c68bd 100644
+index 45eeac9..50bf71c 100644
--- js/src/ion/AsmJSSignalHandlers.cpp
+++ js/src/ion/AsmJSSignalHandlers.cpp
-@@ -352,6 +352,136 @@ SetRegisterToCoercedUndefined(mcontext_t &context, bool isFloat32, AnyRegister r
- }
- }
- # endif
-+# elif defined(__NetBSD__) || defined(__OpenBSD__)
-+# include <machine/mcontext.h>
-+
-+static uint8_t **
-+ContextToPC(mcontext_t &context)
-+{
-+# if defined(JS_CPU_X86)
-+ JS_STATIC_ASSERT(sizeof(context.__gregs[_REG_EIP]) == sizeof(void*));
-+ return reinterpret_cast<uint8_t**>(&context.__gregs[_REG_EIP]);
-+# else
-+ JS_STATIC_ASSERT(sizeof(context.__gregs[_REG_RIP]) == sizeof(void*));
-+ return reinterpret_cast<uint8_t**>(&context.__gregs[_REG_RIP]);
-+# endif
-+}
-+
-+# if defined(JS_CPU_X64)
-+# include <machine/fpu.h>
-+# define fp_xmm(mc,i) (&((struct fxsave64 *)(mc)->__fpregs)->fx_xmm[i])
+@@ -18,6 +18,138 @@ using namespace js::ion;
+
+ #ifdef JS_ASMJS
+
++#if defined(XP_WIN)
++# define XMM_sig(p,i) ((p)->Xmm##i)
++# define EIP_sig(p) ((p)->Eip)
++# define RIP_sig(p) ((p)->Rip)
++# define RAX_sig(p) ((p)->Rax)
++# define RCX_sig(p) ((p)->Rcx)
++# define RDX_sig(p) ((p)->Rdx)
++# define RBX_sig(p) ((p)->Rbx)
++# define RSP_sig(p) ((p)->Rsp)
++# define RBP_sig(p) ((p)->Rbp)
++# define RSI_sig(p) ((p)->Rsi)
++# define RDI_sig(p) ((p)->Rdi)
++# define R8_sig(p) ((p)->R8)
++# define R9_sig(p) ((p)->R9)
++# define R10_sig(p) ((p)->R10)
++# define R11_sig(p) ((p)->R11)
++# define R12_sig(p) ((p)->R12)
++# define R13_sig(p) ((p)->R13)
++# define R14_sig(p) ((p)->R14)
++# define R15_sig(p) ((p)->R15)
++#elif defined(__OpenBSD__)
++# define XMM_sig(p,i) ((p)->sc_fpstate->fx_xmm[i])
++# define EIP_sig(p) ((p)->sc_eip)
++# define RIP_sig(p) ((p)->sc_rip)
++# define RAX_sig(p) ((p)->sc_rax)
++# define RCX_sig(p) ((p)->sc_rcx)
++# define RDX_sig(p) ((p)->sc_rdx)
++# define RBX_sig(p) ((p)->sc_rbx)
++# define RSP_sig(p) ((p)->sc_rsp)
++# define RBP_sig(p) ((p)->sc_rbp)
++# define RSI_sig(p) ((p)->sc_rsi)
++# define RDI_sig(p) ((p)->sc_rdi)
++# define R8_sig(p) ((p)->sc_r8)
++# define R9_sig(p) ((p)->sc_r9)
++# define R10_sig(p) ((p)->sc_r10)
++# define R11_sig(p) ((p)->sc_r11)
++# define R12_sig(p) ((p)->sc_r12)
++# define R13_sig(p) ((p)->sc_r13)
++# define R14_sig(p) ((p)->sc_r14)
++# define R15_sig(p) ((p)->sc_r15)
++#elif defined(__linux__) || defined(SOLARIS)
++# if defined(__linux__)
++# define XMM_sig(p,i) ((p)->uc_mcontext.fpregs->_xmm[i])
++# else
++# define XMM_sig(p,i) ((p)->uc_mcontext.fpregs->xmm[i])
++# endif
++# define EIP_sig(p) ((p)->uc_mcontext.gregs[REG_EIP])
++# define RIP_sig(p) ((p)->uc_mcontext.gregs[REG_RIP])
++# define RAX_sig(p) ((p)->uc_mcontext.gregs[REG_RAX])
++# define RCX_sig(p) ((p)->uc_mcontext.gregs[REG_RCX])
++# define RDX_sig(p) ((p)->uc_mcontext.gregs[REG_RDX])
++# define RBX_sig(p) ((p)->uc_mcontext.gregs[REG_RBX])
++# define RSP_sig(p) ((p)->uc_mcontext.gregs[REG_RSP])
++# define RBP_sig(p) ((p)->uc_mcontext.gregs[REG_RBP])
++# define RSI_sig(p) ((p)->uc_mcontext.gregs[REG_RSI])
++# define RDI_sig(p) ((p)->uc_mcontext.gregs[REG_RDI])
++# define R8_sig(p) ((p)->uc_mcontext.gregs[REG_R8])
++# define R9_sig(p) ((p)->uc_mcontext.gregs[REG_R9])
++# define R10_sig(p) ((p)->uc_mcontext.gregs[REG_R10])
++# define R11_sig(p) ((p)->uc_mcontext.gregs[REG_R11])
++# define R12_sig(p) ((p)->uc_mcontext.gregs[REG_R12])
++# define R13_sig(p) ((p)->uc_mcontext.gregs[REG_R13])
++# define R14_sig(p) ((p)->uc_mcontext.gregs[REG_R14])
++# define R15_sig(p) ((p)->uc_mcontext.gregs[REG_R15])
++#elif defined(__NetBSD__)
++# define XMM_sig(p,i) (((struct fxsave64 *)(p)->uc_mcontext.__fpregs)->fx_xmm[i])
++# define EIP_sig(p) ((p)->uc_mcontext.__gregs[_REG_EIP])
++# define RIP_sig(p) ((p)->uc_mcontext.__gregs[_REG_RIP])
++# define RAX_sig(p) ((p)->uc_mcontext.__gregs[_REG_RAX])
++# define RCX_sig(p) ((p)->uc_mcontext.__gregs[_REG_RCX])
++# define RDX_sig(p) ((p)->uc_mcontext.__gregs[_REG_RDX])
++# define RBX_sig(p) ((p)->uc_mcontext.__gregs[_REG_RBX])
++# define RSP_sig(p) ((p)->uc_mcontext.__gregs[_REG_RSP])
++# define RBP_sig(p) ((p)->uc_mcontext.__gregs[_REG_RBP])
++# define RSI_sig(p) ((p)->uc_mcontext.__gregs[_REG_RSI])
++# define RDI_sig(p) ((p)->uc_mcontext.__gregs[_REG_RDI])
++# define R8_sig(p) ((p)->uc_mcontext.__gregs[_REG_R8])
++# define R9_sig(p) ((p)->uc_mcontext.__gregs[_REG_R9])
++# define R10_sig(p) ((p)->uc_mcontext.__gregs[_REG_R10])
++# define R11_sig(p) ((p)->uc_mcontext.__gregs[_REG_R11])
++# define R12_sig(p) ((p)->uc_mcontext.__gregs[_REG_R12])
++# define R13_sig(p) ((p)->uc_mcontext.__gregs[_REG_R13])
++# define R14_sig(p) ((p)->uc_mcontext.__gregs[_REG_R14])
++# define R15_sig(p) ((p)->uc_mcontext.__gregs[_REG_R15])
++#elif defined(__DragonFly__) || defined(__FreeBSD__)
++# if defined(__DragonFly__)
++# define XMM_sig(p,i) (((union savefpu *)(p)->uc_mcontext.mc_fpregs)->sv_xmm.sv_xmm[i])
++# else
++# define XMM_sig(p,i) (((struct savefpu *)(p)->uc_mcontext.mc_fpstate)->sv_xmm[i])
++# endif
++# define EIP_sig(p) ((p)->uc_mcontext.mc_eip)
++# define RIP_sig(p) ((p)->uc_mcontext.mc_rip)
++# define RAX_sig(p) ((p)->uc_mcontext.mc_rax)
++# define RCX_sig(p) ((p)->uc_mcontext.mc_rcx)
++# define RDX_sig(p) ((p)->uc_mcontext.mc_rdx)
++# define RBX_sig(p) ((p)->uc_mcontext.mc_rbx)
++# define RSP_sig(p) ((p)->uc_mcontext.mc_rsp)
++# define RBP_sig(p) ((p)->uc_mcontext.mc_rbp)
++# define RSI_sig(p) ((p)->uc_mcontext.mc_rsi)
++# define RDI_sig(p) ((p)->uc_mcontext.mc_rdi)
++# define R8_sig(p) ((p)->uc_mcontext.mc_r8)
++# define R9_sig(p) ((p)->uc_mcontext.mc_r9)
++# define R10_sig(p) ((p)->uc_mcontext.mc_r10)
++# define R11_sig(p) ((p)->uc_mcontext.mc_r11)
++# define R12_sig(p) ((p)->uc_mcontext.mc_r12)
++# define R13_sig(p) ((p)->uc_mcontext.mc_r13)
++# define R14_sig(p) ((p)->uc_mcontext.mc_r14)
++# define R15_sig(p) ((p)->uc_mcontext.mc_r15)
++#elif defined(XP_MACOSX)
++# define XMM_sig(p,i) ((p)->uc_mcontext->__fs.__fpu_xmm##i)
++# define EIP_sig(p) ((p)->uc_mcontext->__ss.__eip)
++# define RIP_sig(p) ((p)->uc_mcontext->__ss.__rip)
++# define RAX_sig(p) ((p)->uc_mcontext->__ss.__rax)
++# define RCX_sig(p) ((p)->uc_mcontext->__ss.__rcx)
++# define RDX_sig(p) ((p)->uc_mcontext->__ss.__rdx)
++# define RBX_sig(p) ((p)->uc_mcontext->__ss.__rbx)
++# define RSP_sig(p) ((p)->uc_mcontext->__ss.__rsp)
++# define RBP_sig(p) ((p)->uc_mcontext->__ss.__rbp)
++# define RSI_sig(p) ((p)->uc_mcontext->__ss.__rsi)
++# define RDI_sig(p) ((p)->uc_mcontext->__ss.__rdi)
++# define R8_sig(p) ((p)->uc_mcontext->__ss.__r8)
++# define R9_sig(p) ((p)->uc_mcontext->__ss.__r9)
++# define R10_sig(p) ((p)->uc_mcontext->__ss.__r10)
++# define R11_sig(p) ((p)->uc_mcontext->__ss.__r11)
++# define R12_sig(p) ((p)->uc_mcontext->__ss.__r12)
++# define R13_sig(p) ((p)->uc_mcontext->__ss.__r13)
++# define R14_sig(p) ((p)->uc_mcontext->__ss.__r14)
++# define R15_sig(p) ((p)->uc_mcontext->__ss.__r15)
++#else
++# error "Don't know how to read/write to the thread state via the mcontext_t."
++#endif
+
-+static void
-+SetRegisterToCoercedUndefined(mcontext_t &context, bool isFloat32, AnyRegister reg)
-+{
-+ if (reg.isFloat()) {
-+ switch (reg.fpu().code()) {
-+ case JSC::X86Registers::xmm0: SetXMMRegToNaN(isFloat32, fp_xmm(&context, 0)); break;
-+ case JSC::X86Registers::xmm1: SetXMMRegToNaN(isFloat32, fp_xmm(&context, 1)); break;
-+ case JSC::X86Registers::xmm2: SetXMMRegToNaN(isFloat32, fp_xmm(&context, 2)); break;
-+ case JSC::X86Registers::xmm3: SetXMMRegToNaN(isFloat32, fp_xmm(&context, 3)); break;
-+ case JSC::X86Registers::xmm4: SetXMMRegToNaN(isFloat32, fp_xmm(&context, 4)); break;
-+ case JSC::X86Registers::xmm5: SetXMMRegToNaN(isFloat32, fp_xmm(&context, 5)); break;
-+ case JSC::X86Registers::xmm6: SetXMMRegToNaN(isFloat32, fp_xmm(&context, 6)); break;
-+ case JSC::X86Registers::xmm7: SetXMMRegToNaN(isFloat32, fp_xmm(&context, 7)); break;
-+ case JSC::X86Registers::xmm8: SetXMMRegToNaN(isFloat32, fp_xmm(&context, 8)); break;
-+ case JSC::X86Registers::xmm9: SetXMMRegToNaN(isFloat32, fp_xmm(&context, 9)); break;
-+ case JSC::X86Registers::xmm10: SetXMMRegToNaN(isFloat32, fp_xmm(&context, 10)); break;
-+ case JSC::X86Registers::xmm11: SetXMMRegToNaN(isFloat32, fp_xmm(&context, 11)); break;
-+ case JSC::X86Registers::xmm12: SetXMMRegToNaN(isFloat32, fp_xmm(&context, 12)); break;
-+ case JSC::X86Registers::xmm13: SetXMMRegToNaN(isFloat32, fp_xmm(&context, 13)); break;
-+ case JSC::X86Registers::xmm14: SetXMMRegToNaN(isFloat32, fp_xmm(&context, 14)); break;
-+ case JSC::X86Registers::xmm15: SetXMMRegToNaN(isFloat32, fp_xmm(&context, 15)); break;
-+ default: MOZ_CRASH();
-+ }
-+ } else {
-+ switch (reg.gpr().code()) {
-+ case JSC::X86Registers::eax: context.__gregs[_REG_RAX] = 0; break;
-+ case JSC::X86Registers::ecx: context.__gregs[_REG_RCX] = 0; break;
-+ case JSC::X86Registers::edx: context.__gregs[_REG_RDX] = 0; break;
-+ case JSC::X86Registers::ebx: context.__gregs[_REG_RBX] = 0; break;
-+ case JSC::X86Registers::esp: context.__gregs[_REG_RSP] = 0; break;
-+ case JSC::X86Registers::ebp: context.__gregs[_REG_RBP] = 0; break;
-+ case JSC::X86Registers::esi: context.__gregs[_REG_RSI] = 0; break;
-+ case JSC::X86Registers::edi: context.__gregs[_REG_RDI] = 0; break;
-+ case JSC::X86Registers::r8: context.__gregs[_REG_R8] = 0; break;
-+ case JSC::X86Registers::r9: context.__gregs[_REG_R9] = 0; break;
-+ case JSC::X86Registers::r10: context.__gregs[_REG_R10] = 0; break;
-+ case JSC::X86Registers::r11: context.__gregs[_REG_R11] = 0; break;
-+ case JSC::X86Registers::r12: context.__gregs[_REG_R12] = 0; break;
-+ case JSC::X86Registers::r13: context.__gregs[_REG_R13] = 0; break;
-+ case JSC::X86Registers::r14: context.__gregs[_REG_R14] = 0; break;
-+ case JSC::X86Registers::r15: context.__gregs[_REG_R15] = 0; break;
-+ default: MOZ_CRASH();
-+ }
-+ }
-+}
-+# endif
-+# elif defined(__DragonFly__) || defined(__FreeBSD__)
-+# include <sys/ucontext.h>
+ // Prevent races trying to install the signal handlers.
+ #ifdef JS_THREADSAFE
+ # include "jslock.h"
+@@ -142,66 +274,90 @@ LookupHeapAccess(const AsmJSModule &module, uint8_t *pc)
+
+ # if defined(XP_WIN)
+ # include "jswin.h"
++# else
++# include <signal.h>
++# include <sys/mman.h>
++# endif
+
-+static uint8_t **
-+ContextToPC(mcontext_t &context)
-+{
-+# if defined(JS_CPU_X86)
-+ JS_STATIC_ASSERT(sizeof(context.mc_eip) == sizeof(void*));
-+ return reinterpret_cast<uint8_t**>(&context.mc_eip);
-+# else
-+ JS_STATIC_ASSERT(sizeof(context.mc_rip) == sizeof(void*));
-+ return reinterpret_cast<uint8_t**>(&context.mc_rip);
-+# endif
-+}
++# if defined(__FreeBSD__)
++# include <sys/ucontext.h> // for ucontext_t, mcontext_t
++# endif
+
-+# if defined(JS_CPU_X64)
-+# include <machine/fpu.h>
-+# define mc_xmm(mc,i) (&((struct savefpu *)(mc)->mc_fpstate)->sv_xmm[i])
++# if defined(JS_CPU_X64)
++# if defined(__DragonFly__)
++# include <machine/npx.h> // for union savefpu
++# elif defined(__FreeBSD__)
++# include <machine/fpu.h> // for struct savefpu
++# endif
++# endif
+
-+static void
-+SetRegisterToCoercedUndefined(mcontext_t &context, bool isFloat32, AnyRegister reg)
-+{
-+ if (reg.isFloat()) {
-+ switch (reg.fpu().code()) {
-+ case JSC::X86Registers::xmm0: SetXMMRegToNaN(isFloat32, mc_xmm(&context, 0)); break;
-+ case JSC::X86Registers::xmm1: SetXMMRegToNaN(isFloat32, mc_xmm(&context, 1)); break;
-+ case JSC::X86Registers::xmm2: SetXMMRegToNaN(isFloat32, mc_xmm(&context, 2)); break;
-+ case JSC::X86Registers::xmm3: SetXMMRegToNaN(isFloat32, mc_xmm(&context, 3)); break;
-+ case JSC::X86Registers::xmm4: SetXMMRegToNaN(isFloat32, mc_xmm(&context, 4)); break;
-+ case JSC::X86Registers::xmm5: SetXMMRegToNaN(isFloat32, mc_xmm(&context, 5)); break;
-+ case JSC::X86Registers::xmm6: SetXMMRegToNaN(isFloat32, mc_xmm(&context, 6)); break;
-+ case JSC::X86Registers::xmm7: SetXMMRegToNaN(isFloat32, mc_xmm(&context, 7)); break;
-+ case JSC::X86Registers::xmm8: SetXMMRegToNaN(isFloat32, mc_xmm(&context, 8)); break;
-+ case JSC::X86Registers::xmm9: SetXMMRegToNaN(isFloat32, mc_xmm(&context, 9)); break;
-+ case JSC::X86Registers::xmm10: SetXMMRegToNaN(isFloat32, mc_xmm(&context, 10)); break;
-+ case JSC::X86Registers::xmm11: SetXMMRegToNaN(isFloat32, mc_xmm(&context, 11)); break;
-+ case JSC::X86Registers::xmm12: SetXMMRegToNaN(isFloat32, mc_xmm(&context, 12)); break;
-+ case JSC::X86Registers::xmm13: SetXMMRegToNaN(isFloat32, mc_xmm(&context, 13)); break;
-+ case JSC::X86Registers::xmm14: SetXMMRegToNaN(isFloat32, mc_xmm(&context, 14)); break;
-+ case JSC::X86Registers::xmm15: SetXMMRegToNaN(isFloat32, mc_xmm(&context, 15)); break;
-+ default: MOZ_CRASH();
-+ }
-+ } else {
-+ switch (reg.gpr().code()) {
-+ case JSC::X86Registers::eax: context.mc_rax = 0; break;
-+ case JSC::X86Registers::ecx: context.mc_rcx = 0; break;
-+ case JSC::X86Registers::edx: context.mc_rdx = 0; break;
-+ case JSC::X86Registers::ebx: context.mc_rbx = 0; break;
-+ case JSC::X86Registers::esp: context.mc_rsp = 0; break;
-+ case JSC::X86Registers::ebp: context.mc_rbp = 0; break;
-+ case JSC::X86Registers::esi: context.mc_rsi = 0; break;
-+ case JSC::X86Registers::edi: context.mc_rdi = 0; break;
-+ case JSC::X86Registers::r8: context.mc_r8 = 0; break;
-+ case JSC::X86Registers::r9: context.mc_r9 = 0; break;
-+ case JSC::X86Registers::r10: context.mc_r10 = 0; break;
-+ case JSC::X86Registers::r11: context.mc_r11 = 0; break;
-+ case JSC::X86Registers::r12: context.mc_r12 = 0; break;
-+ case JSC::X86Registers::r13: context.mc_r13 = 0; break;
-+ case JSC::X86Registers::r14: context.mc_r14 = 0; break;
-+ case JSC::X86Registers::r15: context.mc_r15 = 0; break;
-+ default: MOZ_CRASH();
-+ }
-+ }
-+}
-+# endif
- # elif defined(XP_MACOSX)
++# if defined(__OpenBSD__)
++# define CONTEXT sigcontext_t
++# elif !defined(XP_WIN)
++# define CONTEXT ucontext_t
++# endif
+
static uint8_t **
- ContextToPC(mcontext_t context)
+-ContextToPC(PCONTEXT context)
++ContextToPC(CONTEXT *context)
+ {
+-# if defined(JS_CPU_X64)
+- JS_STATIC_ASSERT(sizeof(context->Rip) == sizeof(void*));
+- return reinterpret_cast<uint8_t**>(&context->Rip);
+-# else
+- JS_STATIC_ASSERT(sizeof(context->Eip) == sizeof(void*));
+- return reinterpret_cast<uint8_t**>(&context->Eip);
+-# endif
++# if defined(JS_CPU_X86)
++ JS_STATIC_ASSERT(sizeof(EIP_sig(context)) == sizeof(void*));
++ return reinterpret_cast<uint8_t**>(&EIP_sig(context));
++# else
++ JS_STATIC_ASSERT(sizeof(RIP_sig(context)) == sizeof(void*));
++ return reinterpret_cast<uint8_t**>(&RIP_sig(context));
++# endif
+ }
+
+-# if defined(JS_CPU_X64)
++# if defined(JS_CPU_X64)
+ static void
+ SetRegisterToCoercedUndefined(CONTEXT *context, bool isFloat32, AnyRegister reg)
+ {
+ if (reg.isFloat()) {
+ switch (reg.fpu().code()) {
+- case JSC::X86Registers::xmm0: SetXMMRegToNaN(isFloat32, &context->Xmm0); break;
+- case JSC::X86Registers::xmm1: SetXMMRegToNaN(isFloat32, &context->Xmm1); break;
+- case JSC::X86Registers::xmm2: SetXMMRegToNaN(isFloat32, &context->Xmm2); break;
+- case JSC::X86Registers::xmm3: SetXMMRegToNaN(isFloat32, &context->Xmm3); break;
+- case JSC::X86Registers::xmm4: SetXMMRegToNaN(isFloat32, &context->Xmm4); break;
+- case JSC::X86Registers::xmm5: SetXMMRegToNaN(isFloat32, &context->Xmm5); break;
+- case JSC::X86Registers::xmm6: SetXMMRegToNaN(isFloat32, &context->Xmm6); break;
+- case JSC::X86Registers::xmm7: SetXMMRegToNaN(isFloat32, &context->Xmm7); break;
+- case JSC::X86Registers::xmm8: SetXMMRegToNaN(isFloat32, &context->Xmm8); break;
+- case JSC::X86Registers::xmm9: SetXMMRegToNaN(isFloat32, &context->Xmm9); break;
+- case JSC::X86Registers::xmm10: SetXMMRegToNaN(isFloat32, &context->Xmm10); break;
+- case JSC::X86Registers::xmm11: SetXMMRegToNaN(isFloat32, &context->Xmm11); break;
+- case JSC::X86Registers::xmm12: SetXMMRegToNaN(isFloat32, &context->Xmm12); break;
+- case JSC::X86Registers::xmm13: SetXMMRegToNaN(isFloat32, &context->Xmm13); break;
+- case JSC::X86Registers::xmm14: SetXMMRegToNaN(isFloat32, &context->Xmm14); break;
+- case JSC::X86Registers::xmm15: SetXMMRegToNaN(isFloat32, &context->Xmm15); break;
++ case JSC::X86Registers::xmm0: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 0)); break;
++ case JSC::X86Registers::xmm1: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 1)); break;
++ case JSC::X86Registers::xmm2: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 2)); break;
++ case JSC::X86Registers::xmm3: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 3)); break;
++ case JSC::X86Registers::xmm4: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 4)); break;
++ case JSC::X86Registers::xmm5: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 5)); break;
++ case JSC::X86Registers::xmm6: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 6)); break;
++ case JSC::X86Registers::xmm7: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 7)); break;
++ case JSC::X86Registers::xmm8: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 8)); break;
++ case JSC::X86Registers::xmm9: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 9)); break;
++ case JSC::X86Registers::xmm10: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 10)); break;
++ case JSC::X86Registers::xmm11: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 11)); break;
++ case JSC::X86Registers::xmm12: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 12)); break;
++ case JSC::X86Registers::xmm13: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 13)); break;
++ case JSC::X86Registers::xmm14: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 14)); break;
++ case JSC::X86Registers::xmm15: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 15)); break;
+ default: MOZ_CRASH();
+ }
+ } else {
+ switch (reg.gpr().code()) {
+- case JSC::X86Registers::eax: context->Rax = 0; break;
+- case JSC::X86Registers::ecx: context->Rcx = 0; break;
+- case JSC::X86Registers::edx: context->Rdx = 0; break;
+- case JSC::X86Registers::ebx: context->Rbx = 0; break;
+- case JSC::X86Registers::esp: context->Rsp = 0; break;
+- case JSC::X86Registers::ebp: context->Rbp = 0; break;
+- case JSC::X86Registers::esi: context->Rsi = 0; break;
+- case JSC::X86Registers::edi: context->Rdi = 0; break;
+- case JSC::X86Registers::r8: context->R8 = 0; break;
+- case JSC::X86Registers::r9: context->R9 = 0; break;
+- case JSC::X86Registers::r10: context->R10 = 0; break;
+- case JSC::X86Registers::r11: context->R11 = 0; break;
+- case JSC::X86Registers::r12: context->R12 = 0; break;
+- case JSC::X86Registers::r13: context->R13 = 0; break;
+- case JSC::X86Registers::r14: context->R14 = 0; break;
+- case JSC::X86Registers::r15: context->R15 = 0; break;
++ case JSC::X86Registers::eax: RAX_sig(context) = 0; break;
++ case JSC::X86Registers::ecx: RCX_sig(context) = 0; break;
++ case JSC::X86Registers::edx: RDX_sig(context) = 0; break;
++ case JSC::X86Registers::ebx: RBX_sig(context) = 0; break;
++ case JSC::X86Registers::esp: RSP_sig(context) = 0; break;
++ case JSC::X86Registers::ebp: RBP_sig(context) = 0; break;
++ case JSC::X86Registers::esi: RSI_sig(context) = 0; break;
++ case JSC::X86Registers::edi: RDI_sig(context) = 0; break;
++ case JSC::X86Registers::r8: R8_sig(context) = 0; break;
++ case JSC::X86Registers::r9: R9_sig(context) = 0; break;
++ case JSC::X86Registers::r10: R10_sig(context) = 0; break;
++ case JSC::X86Registers::r11: R11_sig(context) = 0; break;
++ case JSC::X86Registers::r12: R12_sig(context) = 0; break;
++ case JSC::X86Registers::r13: R13_sig(context) = 0; break;
++ case JSC::X86Registers::r14: R14_sig(context) = 0; break;
++ case JSC::X86Registers::r15: R15_sig(context) = 0; break;
+ default: MOZ_CRASH();
+ }
+ }
+ }
+-# endif
++# endif
++
++# if defined(XP_WIN)
+
+ static bool
+ HandleException(PEXCEPTION_POINTERS exception)
+@@ -286,133 +442,7 @@ AsmJSExceptionHandler(LPEXCEPTION_POINTERS exception)
+ return EXCEPTION_CONTINUE_SEARCH;
+ }
+
+-# else // If not Windows, assume Unix
+-# include <signal.h>
+-# include <sys/mman.h>
+-
+-// Unfortunately, we still need OS-specific code to read/write to the thread
+-// state via the mcontext_t.
+-# if defined(__linux__)
+-static uint8_t **
+-ContextToPC(mcontext_t &context)
+-{
+-# if defined(JS_CPU_X86)
+- JS_STATIC_ASSERT(sizeof(context.gregs[REG_EIP]) == sizeof(void*));
+- return reinterpret_cast<uint8_t**>(&context.gregs[REG_EIP]);
+-# else
+- JS_STATIC_ASSERT(sizeof(context.gregs[REG_RIP]) == sizeof(void*));
+- return reinterpret_cast<uint8_t**>(&context.gregs[REG_RIP]);
+-# endif
+-}
+-
+-# if defined(JS_CPU_X64)
+-static void
+-SetRegisterToCoercedUndefined(mcontext_t &context, bool isFloat32, AnyRegister reg)
+-{
+- if (reg.isFloat()) {
+- switch (reg.fpu().code()) {
+- case JSC::X86Registers::xmm0: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[0]); break;
+- case JSC::X86Registers::xmm1: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[1]); break;
+- case JSC::X86Registers::xmm2: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[2]); break;
+- case JSC::X86Registers::xmm3: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[3]); break;
+- case JSC::X86Registers::xmm4: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[4]); break;
+- case JSC::X86Registers::xmm5: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[5]); break;
+- case JSC::X86Registers::xmm6: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[6]); break;
+- case JSC::X86Registers::xmm7: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[7]); break;
+- case JSC::X86Registers::xmm8: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[8]); break;
+- case JSC::X86Registers::xmm9: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[9]); break;
+- case JSC::X86Registers::xmm10: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[10]); break;
+- case JSC::X86Registers::xmm11: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[11]); break;
+- case JSC::X86Registers::xmm12: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[12]); break;
+- case JSC::X86Registers::xmm13: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[13]); break;
+- case JSC::X86Registers::xmm14: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[14]); break;
+- case JSC::X86Registers::xmm15: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[15]); break;
+- default: MOZ_CRASH();
+- }
+- } else {
+- switch (reg.gpr().code()) {
+- case JSC::X86Registers::eax: context.gregs[REG_RAX] = 0; break;
+- case JSC::X86Registers::ecx: context.gregs[REG_RCX] = 0; break;
+- case JSC::X86Registers::edx: context.gregs[REG_RDX] = 0; break;
+- case JSC::X86Registers::ebx: context.gregs[REG_RBX] = 0; break;
+- case JSC::X86Registers::esp: context.gregs[REG_RSP] = 0; break;
+- case JSC::X86Registers::ebp: context.gregs[REG_RBP] = 0; break;
+- case JSC::X86Registers::esi: context.gregs[REG_RSI] = 0; break;
+- case JSC::X86Registers::edi: context.gregs[REG_RDI] = 0; break;
+- case JSC::X86Registers::r8: context.gregs[REG_R8] = 0; break;
+- case JSC::X86Registers::r9: context.gregs[REG_R9] = 0; break;
+- case JSC::X86Registers::r10: context.gregs[REG_R10] = 0; break;
+- case JSC::X86Registers::r11: context.gregs[REG_R11] = 0; break;
+- case JSC::X86Registers::r12: context.gregs[REG_R12] = 0; break;
+- case JSC::X86Registers::r13: context.gregs[REG_R13] = 0; break;
+- case JSC::X86Registers::r14: context.gregs[REG_R14] = 0; break;
+- case JSC::X86Registers::r15: context.gregs[REG_R15] = 0; break;
+- default: MOZ_CRASH();
+- }
+- }
+-}
+-# endif
+-# elif defined(XP_MACOSX)
+-static uint8_t **
+-ContextToPC(mcontext_t context)
+-{
+-# if defined(JS_CPU_X86)
+- JS_STATIC_ASSERT(sizeof(context->__ss.__eip) == sizeof(void*));
+- return reinterpret_cast<uint8_t **>(&context->__ss.__eip);
+-# else
+- JS_STATIC_ASSERT(sizeof(context->__ss.__rip) == sizeof(void*));
+- return reinterpret_cast<uint8_t **>(&context->__ss.__rip);
+-# endif
+-}
+-
+-# if defined(JS_CPU_X64)
+-static void
+-SetRegisterToCoercedUndefined(mcontext_t &context, bool isFloat32, AnyRegister reg)
+-{
+- if (reg.isFloat()) {
+- switch (reg.fpu().code()) {
+- case JSC::X86Registers::xmm0: SetXMMRegToNaN(isFloat32, &context->__fs.__fpu_xmm0); break;
+- case JSC::X86Registers::xmm1: SetXMMRegToNaN(isFloat32, &context->__fs.__fpu_xmm1); break;
+- case JSC::X86Registers::xmm2: SetXMMRegToNaN(isFloat32, &context->__fs.__fpu_xmm2); break;
+- case JSC::X86Registers::xmm3: SetXMMRegToNaN(isFloat32, &context->__fs.__fpu_xmm3); break;
+- case JSC::X86Registers::xmm4: SetXMMRegToNaN(isFloat32, &context->__fs.__fpu_xmm4); break;
+- case JSC::X86Registers::xmm5: SetXMMRegToNaN(isFloat32, &context->__fs.__fpu_xmm5); break;
+- case JSC::X86Registers::xmm6: SetXMMRegToNaN(isFloat32, &context->__fs.__fpu_xmm6); break;
+- case JSC::X86Registers::xmm7: SetXMMRegToNaN(isFloat32, &context->__fs.__fpu_xmm7); break;
+- case JSC::X86Registers::xmm8: SetXMMRegToNaN(isFloat32, &context->__fs.__fpu_xmm8); break;
+- case JSC::X86Registers::xmm9: SetXMMRegToNaN(isFloat32, &context->__fs.__fpu_xmm9); break;
+- case JSC::X86Registers::xmm10: SetXMMRegToNaN(isFloat32, &context->__fs.__fpu_xmm10); break;
+- case JSC::X86Registers::xmm11: SetXMMRegToNaN(isFloat32, &context->__fs.__fpu_xmm11); break;
+- case JSC::X86Registers::xmm12: SetXMMRegToNaN(isFloat32, &context->__fs.__fpu_xmm12); break;
+- case JSC::X86Registers::xmm13: SetXMMRegToNaN(isFloat32, &context->__fs.__fpu_xmm13); break;
+- case JSC::X86Registers::xmm14: SetXMMRegToNaN(isFloat32, &context->__fs.__fpu_xmm14); break;
+- case JSC::X86Registers::xmm15: SetXMMRegToNaN(isFloat32, &context->__fs.__fpu_xmm15); break;
+- default: MOZ_CRASH();
+- }
+- } else {
+- switch (reg.gpr().code()) {
+- case JSC::X86Registers::eax: context->__ss.__rax = 0; break;
+- case JSC::X86Registers::ecx: context->__ss.__rcx = 0; break;
+- case JSC::X86Registers::edx: context->__ss.__rdx = 0; break;
+- case JSC::X86Registers::ebx: context->__ss.__rbx = 0; break;
+- case JSC::X86Registers::esp: context->__ss.__rsp = 0; break;
+- case JSC::X86Registers::ebp: context->__ss.__rbp = 0; break;
+- case JSC::X86Registers::esi: context->__ss.__rsi = 0; break;
+- case JSC::X86Registers::edi: context->__ss.__rdi = 0; break;
+- case JSC::X86Registers::r8: context->__ss.__r8 = 0; break;
+- case JSC::X86Registers::r9: context->__ss.__r9 = 0; break;
+- case JSC::X86Registers::r10: context->__ss.__r10 = 0; break;
+- case JSC::X86Registers::r11: context->__ss.__r11 = 0; break;
+- case JSC::X86Registers::r12: context->__ss.__r12 = 0; break;
+- case JSC::X86Registers::r13: context->__ss.__r13 = 0; break;
+- case JSC::X86Registers::r14: context->__ss.__r14 = 0; break;
+- case JSC::X86Registers::r15: context->__ss.__r15 = 0; break;
+- default: MOZ_CRASH();
+- }
+- }
+-}
+-# endif
+-# endif // end of OS-specific mcontext accessors
++# else // assume XP_UNIX
+
+ // Be very cautious and default to not handling; we don't want to accidentally
+ // silence real crashes from real bugs.
+@@ -423,7 +453,7 @@ HandleSignal(int signum, siginfo_t *info, void *ctx)
+ if (!activation)
+ return false;
+
+- mcontext_t &context = reinterpret_cast<ucontext_t*>(ctx)->uc_mcontext;
++ CONTEXT *context = (CONTEXT *)ctx;
+ uint8_t **ppc = ContextToPC(context);
+ uint8_t *pc = *ppc;
+
diff --git js/src/ion/x64/Assembler-x64.cpp js/src/ion/x64/Assembler-x64.cpp
-index 9984777..0ab0891 100644
+index 9984777..8b06a55 100644
--- js/src/ion/x64/Assembler-x64.cpp
+++ js/src/ion/x64/Assembler-x64.cpp
@@ -49,7 +49,7 @@ ABIArgGenerator::next(MIRType type)
@@ -161,7 +443,16 @@
}
return current_;
-#elif defined(XP_MACOSX) || defined(__linux__)
-+#elif defined(XP_MACOSX) || defined(__linux__) || defined(__DragonFly__) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__)
++#else // assume XP_UNIX
switch (type) {
case MIRType_Int32:
case MIRType_Pointer:
+@@ -72,8 +72,6 @@ ABIArgGenerator::next(MIRType type)
+ JS_NOT_REACHED("Unexpected argument type");
+ }
+ return current_;
+-#else
+-# error "Missing ABI"
+ #endif
+ }
+
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