Date: Thu, 15 May 2014 15:47:52 +0000 (UTC) From: Luiz Otavio O Souza <loos@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r266148 - in stable/10/sys/arm/ti: . am335x Message-ID: <201405151547.s4FFlqY7059185@svn.freebsd.org>
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Author: loos Date: Thu May 15 15:47:52 2014 New Revision: 266148 URL: http://svnweb.freebsd.org/changeset/base/266148 Log: MFC r259125, r264019, r264083, r264153, r264197 r259125: Fix a few typos on the scm (control module) pin mux definitions. r264019: Fix some of the style(9) problems on ti_gpio. Remove redundant code and declarations. r264083: Move the GPIO bank initialization to a new function to make easier to detect errors. Reset the GPIO module during the initialization. This is guaranteed to be the same as a hardware reset. Tested on AM335x (BBB) and checked against the omap3 and omap4 TRM. Do a better job freeing resources when there are errors and on ti_gpio_detach(). r264153: - Fix the setup of interrupts for banks 2 and 3 on AM335x. On AM335x each one of the four GPIO banks has two physical interrupt lines, so we now allocate resources and setup our interrupt handler for all the (8) available interrupts. On OMAP3 and OMAP4 there is only one interrupt for each GPIO bank (6 banks, 6 interrupts), but there are two set of registers where the first one is used to setup the delivery of interrupts to the MPU and the second set, setup the delivery of interrupts to the DSP. On AM335x, each set of registers controls each one of the interrupt lines. - Remove nonexistent registers for OMAP4 and AM335x, replace their use with the correct ones for these SoCs. - Remove stray whitespace. r264197: Partially revert r264083. While it is the recommended initialization procedure, it hangs on the reset of the second GPIO module on pandaboard. Removes the module reset for now as more investigation is needed. Modified: stable/10/sys/arm/ti/am335x/am335x_scm_padconf.c stable/10/sys/arm/ti/ti_gpio.c Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/arm/ti/am335x/am335x_scm_padconf.c ============================================================================== --- stable/10/sys/arm/ti/am335x/am335x_scm_padconf.c Thu May 15 15:45:45 2014 (r266147) +++ stable/10/sys/arm/ti/am335x/am335x_scm_padconf.c Thu May 15 15:47:52 2014 (r266148) @@ -170,8 +170,8 @@ const struct ti_scm_padconf ti_padconf_d _PIN(0x948, "MDIO", 0, 7, "mdio_data", "timer6", "uart5_rxd", "uart3_ctsn", "mmc0_sdcd","mmc1_cmd", "mmc2_cmd","gpio0_0"), _PIN(0x94c, "MDC", 1, 7, "mdio_clk", "timer5", "uart5_txd", "uart3_rtsn", "mmc0_sdwp", "mmc1_clk", "mmc2_clk", "gpio0_1"), _PIN(0x950, "SPI0_SCLK", 2, 7, "spi0_sclk", "uart2_rxd", "I2C2_SDA", "ehrpwm0A", "pr1_uart0_cts_n", "pr1_edio_sof", "EMU2", "gpio0_2"), - _PIN(0x954, "SPI0_D0", 3, 7, "spi0_d0", "uart2_txd", "i2C2_SCL", "ehrpwm0B", "pr1_uart0_rts_n", "pr1_edio_latch_in", "EMU3", "gpio0_3"), - _PIN(0x958, "SPIO_D1", 4, 7, "spi0_d1", "mmc1_sdwp", "I2C1_SDA", "ehrpwm0_tripzone_input", "pr1_uart0_rxd", "pr1_edio_data_in0", "pr1_edio_data_out0", "gpio0_4"), + _PIN(0x954, "SPI0_D0", 3, 7, "spi0_d0", "uart2_txd", "I2C2_SCL", "ehrpwm0B", "pr1_uart0_rts_n", "pr1_edio_latch_in", "EMU3", "gpio0_3"), + _PIN(0x958, "SPI0_D1", 4, 7, "spi0_d1", "mmc1_sdwp", "I2C1_SDA", "ehrpwm0_tripzone_input", "pr1_uart0_rxd", "pr1_edio_data_in0", "pr1_edio_data_out0", "gpio0_4"), _PIN(0x95c, "SPI0_CS0", 5, 7, "spi0_cs0", "mmc2_sdwp", "I2C1_SCL", "ehrpwm0_synci", "pr1_uart0_txd", "pr1_edio_data_in1", "pr1_edio_data_out1", "gpio0_5"), _PIN(0x960, "SPI0_CS1", 6, 7, "spi0_cs1", "uart3_rxd", "eCAP1_in_PWM1_out", "mcc0_pow", "xdm_event_intr2", "mmc0_sdcd", "EMU4", "gpio0_6"), _PIN(0x964, "ECAP0_IN_PWM0_OUT",7, 7, "eCAP0_in_PWM0_out", "uart3_txd", "spi1_cs1", "pr1_ecap0_ecap_capin_apwm_o", "spi1_sclk", "mmc0_sdwp", "xdma_event_intr2", "gpio0_7"), @@ -180,7 +180,7 @@ const struct ti_scm_padconf ti_padconf_d _PIN(0x970, "UART0_rxd", 42, 7, "uart0_rxd", "spi1_cs0", "dcan0_tx", "I2C2_SDA", "eCAP2_in_PWM2_out", "pr1_pru1_pru_r30_14", "pr1_pru1_pru_r31_14", "gpio1_10"), _PIN(0x974, "UART0_txd", 43, 7, "uart0_txd", "spi1_cs1", "dcan0_rx", "I2C2_SCL", "eCAP1_in_PWM1_out", "pr1_pru1_pru_r30_15", "pr1_pru1_pru_r31_15", "gpio1_11"), _PIN(0x978, "UART1_CTSn", 12, 7, "uart1_ctsn", "timer6_mux1", "dcan0_tx", "I2C2_SDA", "spi1_cs0", "pr1_uart0_cts_n", "pr1_edc_latch0_in", "gpio0_12"), - _PIN(0x97c, "UART1_RTSn", 13, 7, "uart1_rtsn", "timer5_mux1", "dcan0_rx", "I2C2_SCL", "spi1_cs1", "pr1_uart0_rts_n ", "pr1_edc_latch1_in", "gpio0_13"), + _PIN(0x97c, "UART1_RTSn", 13, 7, "uart1_rtsn", "timer5_mux1", "dcan0_rx", "I2C2_SCL", "spi1_cs1", "pr1_uart0_rts_n", "pr1_edc_latch1_in", "gpio0_13"), _PIN(0x980, "UART1_RXD", 14, 7, "uart1_rxd", "mmc1_sdwp", "dcan1_tx", "I2C1_SDA", NULL, "pr1_uart0_rxd", "pr1_pru1_pru_r31_16", "gpio0_14"), _PIN(0x984, "UART1_TXD", 15, 7, "uart1_txd", "mmc2_sdwp", "dcan1_rx", "I2C1_SCL", NULL, "pr1_uart0_txd", "pr1_pru0_pru_r31_16", "gpio0_15"), _PIN(0x988, "I2C0_SDA", 101, 7, "I2C0_SDA", "timer4", "uart2_ctsn", "eCAP2_in_PWM2_out", NULL, NULL, NULL, "gpio3_5"), Modified: stable/10/sys/arm/ti/ti_gpio.c ============================================================================== --- stable/10/sys/arm/ti/ti_gpio.c Thu May 15 15:45:45 2014 (r266147) +++ stable/10/sys/arm/ti/ti_gpio.c Thu May 15 15:47:52 2014 (r266148) @@ -66,92 +66,88 @@ __FBSDID("$FreeBSD$"); #include "gpio_if.h" - /* Register definitions */ -#define TI_GPIO_REVISION 0x0000 -#define TI_GPIO_SYSCONFIG 0x0010 +/* Register definitions */ +#define TI_GPIO_REVISION 0x0000 +#define TI_GPIO_SYSCONFIG 0x0010 #if defined(SOC_OMAP3) -#define TI_GPIO_REVISION 0x0000 -#define TI_GPIO_SYSCONFIG 0x0010 -#define TI_GPIO_SYSSTATUS 0x0014 -#define TI_GPIO_IRQSTATUS1 0x0018 -#define TI_GPIO_IRQENABLE1 0x001C -#define TI_GPIO_WAKEUPENABLE 0x0020 -#define TI_GPIO_IRQSTATUS2 0x0028 -#define TI_GPIO_IRQENABLE2 0x002C -#define TI_GPIO_CTRL 0x0030 -#define TI_GPIO_OE 0x0034 -#define TI_GPIO_DATAIN 0x0038 -#define TI_GPIO_DATAOUT 0x003C -#define TI_GPIO_LEVELDETECT0 0x0040 -#define TI_GPIO_LEVELDETECT1 0x0044 -#define TI_GPIO_RISINGDETECT 0x0048 -#define TI_GPIO_FALLINGDETECT 0x004C -#define TI_GPIO_DEBOUNCENABLE 0x0050 -#define TI_GPIO_DEBOUNCINGTIME 0x0054 -#define TI_GPIO_CLEARIRQENABLE1 0x0060 -#define TI_GPIO_SETIRQENABLE1 0x0064 -#define TI_GPIO_CLEARIRQENABLE2 0x0070 -#define TI_GPIO_SETIRQENABLE2 0x0074 -#define TI_GPIO_CLEARWKUENA 0x0080 -#define TI_GPIO_SETWKUENA 0x0084 -#define TI_GPIO_CLEARDATAOUT 0x0090 -#define TI_GPIO_SETDATAOUT 0x0094 +#define TI_GPIO_SYSSTATUS 0x0014 +#define TI_GPIO_IRQSTATUS1 0x0018 +#define TI_GPIO_IRQENABLE1 0x001C +#define TI_GPIO_WAKEUPENABLE 0x0020 +#define TI_GPIO_IRQSTATUS2 0x0028 +#define TI_GPIO_IRQENABLE2 0x002C +#define TI_GPIO_CTRL 0x0030 +#define TI_GPIO_OE 0x0034 +#define TI_GPIO_DATAIN 0x0038 +#define TI_GPIO_DATAOUT 0x003C +#define TI_GPIO_LEVELDETECT0 0x0040 +#define TI_GPIO_LEVELDETECT1 0x0044 +#define TI_GPIO_RISINGDETECT 0x0048 +#define TI_GPIO_FALLINGDETECT 0x004C +#define TI_GPIO_DEBOUNCENABLE 0x0050 +#define TI_GPIO_DEBOUNCINGTIME 0x0054 +#define TI_GPIO_CLEARIRQENABLE1 0x0060 +#define TI_GPIO_SETIRQENABLE1 0x0064 +#define TI_GPIO_CLEARIRQENABLE2 0x0070 +#define TI_GPIO_SETIRQENABLE2 0x0074 +#define TI_GPIO_CLEARWKUENA 0x0080 +#define TI_GPIO_SETWKUENA 0x0084 +#define TI_GPIO_CLEARDATAOUT 0x0090 +#define TI_GPIO_SETDATAOUT 0x0094 #elif defined(SOC_OMAP4) || defined(SOC_TI_AM335X) -#define TI_GPIO_IRQSTATUS_RAW_0 0x0024 -#define TI_GPIO_IRQSTATUS_RAW_1 0x0028 -#define TI_GPIO_IRQSTATUS_0 0x002C -#define TI_GPIO_IRQSTATUS_1 0x0030 -#define TI_GPIO_IRQSTATUS_SET_0 0x0034 -#define TI_GPIO_IRQSTATUS_SET_1 0x0038 -#define TI_GPIO_IRQSTATUS_CLR_0 0x003C -#define TI_GPIO_IRQSTATUS_CLR_1 0x0040 -#define TI_GPIO_IRQWAKEN_0 0x0044 -#define TI_GPIO_IRQWAKEN_1 0x0048 -#define TI_GPIO_SYSSTATUS 0x0114 -#define TI_GPIO_IRQSTATUS1 0x0118 -#define TI_GPIO_IRQENABLE1 0x011C -#define TI_GPIO_WAKEUPENABLE 0x0120 -#define TI_GPIO_IRQSTATUS2 0x0128 -#define TI_GPIO_IRQENABLE2 0x012C -#define TI_GPIO_CTRL 0x0130 -#define TI_GPIO_OE 0x0134 -#define TI_GPIO_DATAIN 0x0138 -#define TI_GPIO_DATAOUT 0x013C -#define TI_GPIO_LEVELDETECT0 0x0140 -#define TI_GPIO_LEVELDETECT1 0x0144 -#define TI_GPIO_RISINGDETECT 0x0148 -#define TI_GPIO_FALLINGDETECT 0x014C -#define TI_GPIO_DEBOUNCENABLE 0x0150 -#define TI_GPIO_DEBOUNCINGTIME 0x0154 -#define TI_GPIO_CLEARIRQENABLE1 0x0160 -#define TI_GPIO_SETIRQENABLE1 0x0164 -#define TI_GPIO_CLEARIRQENABLE2 0x0170 -#define TI_GPIO_SETIRQENABLE2 0x0174 -#define TI_GPIO_CLEARWKUPENA 0x0180 -#define TI_GPIO_SETWKUENA 0x0184 -#define TI_GPIO_CLEARDATAOUT 0x0190 -#define TI_GPIO_SETDATAOUT 0x0194 +#define TI_GPIO_IRQSTATUS_RAW_0 0x0024 +#define TI_GPIO_IRQSTATUS_RAW_1 0x0028 +#define TI_GPIO_IRQSTATUS_0 0x002C +#define TI_GPIO_IRQSTATUS_1 0x0030 +#define TI_GPIO_IRQSTATUS_SET_0 0x0034 +#define TI_GPIO_IRQSTATUS_SET_1 0x0038 +#define TI_GPIO_IRQSTATUS_CLR_0 0x003C +#define TI_GPIO_IRQSTATUS_CLR_1 0x0040 +#define TI_GPIO_IRQWAKEN_0 0x0044 +#define TI_GPIO_IRQWAKEN_1 0x0048 +#define TI_GPIO_SYSSTATUS 0x0114 +#define TI_GPIO_IRQSTATUS1 0x0118 +#define TI_GPIO_IRQENABLE1 0x011C +#define TI_GPIO_WAKEUPENABLE 0x0120 +#define TI_GPIO_IRQSTATUS2 0x0128 +#define TI_GPIO_IRQENABLE2 0x012C +#define TI_GPIO_CTRL 0x0130 +#define TI_GPIO_OE 0x0134 +#define TI_GPIO_DATAIN 0x0138 +#define TI_GPIO_DATAOUT 0x013C +#define TI_GPIO_LEVELDETECT0 0x0140 +#define TI_GPIO_LEVELDETECT1 0x0144 +#define TI_GPIO_RISINGDETECT 0x0148 +#define TI_GPIO_FALLINGDETECT 0x014C +#define TI_GPIO_DEBOUNCENABLE 0x0150 +#define TI_GPIO_DEBOUNCINGTIME 0x0154 +#define TI_GPIO_CLEARWKUPENA 0x0180 +#define TI_GPIO_SETWKUENA 0x0184 +#define TI_GPIO_CLEARDATAOUT 0x0190 +#define TI_GPIO_SETDATAOUT 0x0194 #else #error "Unknown SoC" #endif - /*Other SoC Specific definitions*/ +/* Other SoC Specific definitions */ #if defined(SOC_OMAP3) -#define MAX_GPIO_BANKS 6 -#define FIRST_GPIO_BANK 1 -#define PINS_PER_BANK 32 -#define TI_GPIO_REV 0x00000025 +#define MAX_GPIO_BANKS 6 +#define FIRST_GPIO_BANK 1 +#define INTR_PER_BANK 1 +#define TI_GPIO_REV 0x00000025 #elif defined(SOC_OMAP4) -#define MAX_GPIO_BANKS 6 -#define FIRST_GPIO_BANK 1 -#define PINS_PER_BANK 32 -#define TI_GPIO_REV 0x50600801 +#define MAX_GPIO_BANKS 6 +#define FIRST_GPIO_BANK 1 +#define INTR_PER_BANK 1 +#define TI_GPIO_REV 0x50600801 #elif defined(SOC_TI_AM335X) -#define MAX_GPIO_BANKS 4 -#define FIRST_GPIO_BANK 0 -#define PINS_PER_BANK 32 -#define TI_GPIO_REV 0x50600801 +#define MAX_GPIO_BANKS 4 +#define FIRST_GPIO_BANK 0 +#define INTR_PER_BANK 2 +#define TI_GPIO_REV 0x50600801 #endif +#define PINS_PER_BANK 32 +#define MAX_GPIO_INTRS MAX_GPIO_BANKS * INTR_PER_BANK /** * ti_gpio_mem_spec - Resource specification used when allocating resources @@ -159,6 +155,15 @@ __FBSDID("$FreeBSD$"); * * This driver module can have up to six independent memory regions, each * region typically controls 32 GPIO pins. + * + * On OMAP3 and OMAP4 there is only one physical interrupt line per bank, + * but there are two set of registers which control the interrupt delivery + * to internal subsystems. The first set of registers control the + * interrupts delivery to the MPU and the second set control the + * interrupts delivery to the DSP. + * + * On AM335x there are two physical interrupt lines for each GPIO module. + * Each interrupt line is controlled by a set of registers. */ static struct resource_spec ti_gpio_mem_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, @@ -176,9 +181,11 @@ static struct resource_spec ti_gpio_irq_ { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL }, { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL }, { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL }, -#if !defined(SOC_TI_AM335X) { SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL }, { SYS_RES_IRQ, 5, RF_ACTIVE | RF_OPTIONAL }, +#if defined(SOC_TI_AM335X) + { SYS_RES_IRQ, 6, RF_ACTIVE | RF_OPTIONAL }, + { SYS_RES_IRQ, 7, RF_ACTIVE | RF_OPTIONAL }, #endif { -1, 0, 0 } }; @@ -189,34 +196,38 @@ static struct resource_spec ti_gpio_irq_ * This structure is allocated during driver attach. */ struct ti_gpio_softc { - device_t sc_dev; + device_t sc_dev; - /* The memory resource(s) for the PRCM register set, when the device is - * created the caller can assign up to 4 memory regions. + /* + * The memory resource(s) for the PRCM register set, when the device is + * created the caller can assign up to 6 memory regions depending on + * the SoC type. */ - struct resource* sc_mem_res[MAX_GPIO_BANKS]; - struct resource* sc_irq_res[MAX_GPIO_BANKS]; + struct resource *sc_mem_res[MAX_GPIO_BANKS]; + struct resource *sc_irq_res[MAX_GPIO_INTRS]; - /* The handle for the register IRQ handlers */ - void* sc_irq_hdl[MAX_GPIO_BANKS]; + /* The handle for the register IRQ handlers. */ + void *sc_irq_hdl[MAX_GPIO_INTRS]; - /* The following describes the H/W revision of each of the GPIO banks */ - uint32_t sc_revision[MAX_GPIO_BANKS]; + /* + * The following describes the H/W revision of each of the GPIO banks. + */ + uint32_t sc_revision[MAX_GPIO_BANKS]; - struct mtx sc_mtx; + struct mtx sc_mtx; }; /** * Macros for driver mutex locking */ -#define TI_GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) -#define TI_GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) -#define TI_GPIO_LOCK_INIT(_sc) \ +#define TI_GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) +#define TI_GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) +#define TI_GPIO_LOCK_INIT(_sc) \ mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ - "ti_gpio", MTX_DEF) -#define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); -#define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); -#define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); + "ti_gpio", MTX_DEF) +#define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx) +#define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED) +#define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED) /** * ti_gpio_read_4 - reads a 16-bit value from one of the PADCONFS registers @@ -251,6 +262,20 @@ ti_gpio_write_4(struct ti_gpio_softc *sc bus_write_4(sc->sc_mem_res[bank], off, val); } +static inline void +ti_gpio_intr_clr(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask) +{ + + /* We clear both set of registers. */ +#if defined(SOC_OMAP4) || defined(SOC_TI_AM335X) + ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_0, mask); + ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_1, mask); +#else + ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE1, mask); + ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE2, mask); +#endif +} + /** * ti_gpio_pin_max - Returns the maximum number of GPIO pins * @dev: gpio device handle @@ -441,7 +466,6 @@ ti_gpio_pin_setflags(device_t dev, uint3 (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) return (EINVAL); - TI_GPIO_LOCK(sc); /* Sanity check the pin number is valid */ @@ -464,7 +488,6 @@ ti_gpio_pin_setflags(device_t dev, uint3 reg_val &= ~mask; ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_val); - TI_GPIO_UNLOCK(sc); return (0); @@ -631,6 +654,97 @@ ti_gpio_probe(device_t dev) return (ENXIO); device_set_desc(dev, "TI General Purpose I/O (GPIO)"); + + return (0); +} + +static int +ti_gpio_attach_intr(device_t dev) +{ + int i; + struct ti_gpio_softc *sc; + + sc = device_get_softc(dev); + for (i = 0; i < MAX_GPIO_INTRS; i++) { + if (sc->sc_irq_res[i] == NULL) + break; + + /* + * Register our interrupt handler for each of the IRQ resources. + */ + if (bus_setup_intr(dev, sc->sc_irq_res[i], + INTR_TYPE_MISC | INTR_MPSAFE, NULL, ti_gpio_intr, sc, + &sc->sc_irq_hdl[i]) != 0) { + device_printf(dev, + "WARNING: unable to register interrupt handler\n"); + return (-1); + } + } + + return (0); +} + +static int +ti_gpio_detach_intr(device_t dev) +{ + int i; + struct ti_gpio_softc *sc; + + /* Teardown our interrupt handlers. */ + sc = device_get_softc(dev); + for (i = 0; i < MAX_GPIO_INTRS; i++) { + if (sc->sc_irq_res[i] == NULL) + break; + + if (sc->sc_irq_hdl[i]) { + bus_teardown_intr(dev, sc->sc_irq_res[i], + sc->sc_irq_hdl[i]); + } + } + + return (0); +} + +static int +ti_gpio_bank_init(device_t dev, int bank) +{ + int pin; + struct ti_gpio_softc *sc; + uint32_t flags, reg_oe; + + sc = device_get_softc(dev); + + /* Enable the interface and functional clocks for the module. */ + ti_prcm_clk_enable(GPIO0_CLK + FIRST_GPIO_BANK + bank); + + /* + * Read the revision number of the module. TI don't publish the + * actual revision numbers, so instead the values have been + * determined by experimentation. + */ + sc->sc_revision[bank] = ti_gpio_read_4(sc, bank, TI_GPIO_REVISION); + + /* Check the revision. */ + if (sc->sc_revision[bank] != TI_GPIO_REV) { + device_printf(dev, "Warning: could not determine the revision " + "of %u GPIO module (revision:0x%08x)\n", + bank, sc->sc_revision[bank]); + return (EINVAL); + } + + /* Disable interrupts for all pins. */ + ti_gpio_intr_clr(sc, bank, 0xffffffff); + + /* Init OE register based on pads configuration. */ + reg_oe = 0xffffffff; + for (pin = 0; pin < PINS_PER_BANK; pin++) { + ti_scm_padconf_get_gpioflags(PINS_PER_BANK * bank + pin, + &flags); + if (flags & GPIO_PIN_OUTPUT) + reg_oe &= ~(1UL << pin); + } + ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_oe); + return (0); } @@ -650,90 +764,56 @@ ti_gpio_probe(device_t dev) static int ti_gpio_attach(device_t dev) { - struct ti_gpio_softc *sc = device_get_softc(dev); + struct ti_gpio_softc *sc; unsigned int i; - int err = 0; - int pin; - uint32_t flags; - uint32_t reg_oe; + int err; + sc = device_get_softc(dev); sc->sc_dev = dev; TI_GPIO_LOCK_INIT(sc); - /* There are up to 6 different GPIO register sets located in different * memory areas on the chip. The memory range should have been set for * the driver when it was added as a child. */ - err = bus_alloc_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res); - if (err) { + if (bus_alloc_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res) != 0) { device_printf(dev, "Error: could not allocate mem resources\n"); return (ENXIO); } /* Request the IRQ resources */ - err = bus_alloc_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res); - if (err) { + if (bus_alloc_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res) != 0) { + bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res); device_printf(dev, "Error: could not allocate irq resources\n"); return (ENXIO); } /* Setup the IRQ resources */ - for (i = 0; i < MAX_GPIO_BANKS; i++) { - if (sc->sc_irq_res[i] == NULL) - break; - - /* Register an interrupt handler for each of the IRQ resources */ - if ((bus_setup_intr(dev, sc->sc_irq_res[i], INTR_TYPE_MISC | INTR_MPSAFE, - NULL, ti_gpio_intr, sc, &(sc->sc_irq_hdl[i])))) { - device_printf(dev, "WARNING: unable to register interrupt handler\n"); - return (ENXIO); - } + if (ti_gpio_attach_intr(dev) != 0) { + ti_gpio_detach_intr(dev); + bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res); + bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res); + return (ENXIO); } - /* Store the device handle back in the sc */ - sc->sc_dev = dev; - /* We need to go through each block and ensure the clocks are running and * the module is enabled. It might be better to do this only when the * pins are configured which would result in less power used if the GPIO * pins weren't used ... */ - for (i = 0; i < MAX_GPIO_BANKS; i++) { + for (i = 0; i < MAX_GPIO_BANKS; i++) { if (sc->sc_mem_res[i] != NULL) { - - /* Enable the interface and functional clocks for the module */ - ti_prcm_clk_enable(GPIO0_CLK + FIRST_GPIO_BANK + i); - - /* Read the revision number of the module. TI don't publish the - * actual revision numbers, so instead the values have been - * determined by experimentation. - */ - sc->sc_revision[i] = ti_gpio_read_4(sc, i, TI_GPIO_REVISION); - - /* Check the revision */ - if (sc->sc_revision[i] != TI_GPIO_REV) { - device_printf(dev, "Warning: could not determine the revision" - "of %u GPIO module (revision:0x%08x)\n", - i, sc->sc_revision[i]); - continue; + /* Initialize the GPIO module. */ + err = ti_gpio_bank_init(dev, i); + if (err != 0) { + ti_gpio_detach_intr(dev); + bus_release_resources(dev, ti_gpio_irq_spec, + sc->sc_irq_res); + bus_release_resources(dev, ti_gpio_mem_spec, + sc->sc_mem_res); + return (err); } - - /* Disable interrupts for all pins */ - ti_gpio_write_4(sc, i, TI_GPIO_CLEARIRQENABLE1, 0xffffffff); - ti_gpio_write_4(sc, i, TI_GPIO_CLEARIRQENABLE2, 0xffffffff); - - /* Init OE register based on pads configuration */ - reg_oe = 0xffffffff; - for (pin = 0; pin < 32; pin++) { - ti_scm_padconf_get_gpioflags( - PINS_PER_BANK*i + pin, &flags); - if (flags & GPIO_PIN_OUTPUT) - reg_oe &= ~(1U << pin); - } - - ti_gpio_write_4(sc, i, TI_GPIO_OE, reg_oe); } } @@ -766,26 +846,21 @@ ti_gpio_detach(device_t dev) KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized")); /* Disable all interrupts */ - for (i = 0; i < MAX_GPIO_BANKS; i++) { - if (sc->sc_mem_res[i] != NULL) { - ti_gpio_write_4(sc, i, TI_GPIO_CLEARIRQENABLE1, 0xffffffff); - ti_gpio_write_4(sc, i, TI_GPIO_CLEARIRQENABLE2, 0xffffffff); - } + for (i = 0; i < MAX_GPIO_BANKS; i++) { + if (sc->sc_mem_res[i] != NULL) + ti_gpio_intr_clr(sc, i, 0xffffffff); } bus_generic_detach(dev); - /* Release the memory and IRQ resources */ - for (i = 0; i < MAX_GPIO_BANKS; i++) { - if (sc->sc_mem_res[i] != NULL) - bus_release_resource(dev, SYS_RES_MEMORY, i, sc->sc_mem_res[i]); - if (sc->sc_irq_res[i] != NULL) - bus_release_resource(dev, SYS_RES_IRQ, i, sc->sc_irq_res[i]); - } + /* Release the memory and IRQ resources. */ + ti_gpio_detach_intr(dev); + bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res); + bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res); TI_GPIO_LOCK_DESTROY(sc); - return(0); + return (0); } static phandle_t
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