Date: Tue, 07 Oct 1997 17:12:46 -0700 From: Ted Faber <faber@ISI.EDU> To: freebsd-hackers@FreeBsd.org Cc: faber@ISI.EDU Subject: patch for PCMCIA support on Hitachi Mx133 Message-ID: <199710080012.RAA06115@vermouth.isi.edu>
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The following patch is allows the use of a Cirrus Logic PD6832 Cardbus PCMCIA controller chip in 16 bit legacy mode. It's relative to a PAO kernel based directly on 2.2.2-RELEASE (the PAO release is PAO-970616 which is available from http://www.jp.FreeBSD.org/PAO/). Although I occasionally patch things when I need the functionality, I don't mirror current or stable, which is why this patch is from these sources. The patches are small, so they should be easy to integrate with PCI support in pcic.c , if there is any forthcoming. The sources must be compiled with the PAO kernel option PCIC_NOCLRREGS enables. I realize that it might be impossible for this patch to get integrated in the main FreeBSD tree, but for folks with Hitcachis, it may be useful. I've sent a copy to Tatsumi Hosokawa as well so that he can add it to the next PAO distribution as well. I've checked the code on my Hitachi with a few cards, and it's worked fine, but that's the extent of my testing. Let the buyer beware. The patch is relative to /usr/src/sys on a 2.2.2-RELEASE kernel with the PAO-970616 patch applied. *** pccard/pcic.c.orig Mon Oct 6 14:04:10 1997 --- pccard/pcic.c Mon Oct 6 14:48:09 1997 *************** *** 107,112 **** --- 107,122 ---- #define PCI_DEVICE_ID_PCIC_CLPD6729 0x11001013ul #define PCI_DEVICE_ID_PCIC_O2MICRO 0x673a1217ul + /* PD6832 defines (should be in a separate file) --- tvf */ + #define PD6832_IO_BASE0 0x002c + #define PD6832_IO_LIMIT0 0x0030 + #define PD6832_IO_BASE1 0x0034 + #define PD6832_IO_LIMIT1 0x0038 + #define PD6832_BRIDGE_CONTROL 0x003c + #define PD6832_SOCKET 0x004c + #define PD6832_BCR_MGMT_IRQ_ENA 0x08000000 + #define PD6832_BCR_ISA_IRQ 0x00800000 + /* end of 6832 defines */ DATA_SET (pcidevice_set, pcic_pci_driver); *************** *** 138,153 **** int i,j; u_char *p; u_long *pl; switch (pcic_pci_id) { case PCI_DEVICE_ID_PCIC_TI1130_CARDBUS: - case PCI_DEVICE_ID_PCIC_CLPD6832_CARDBUS: pcic_pci_ioaddr = pci_conf_read(tag, CARDBUS_LEGACY_16BIT_IOADDR) & ~PCI_MAP_IO; printf("CardBus: Legacy PC-card 16bit I/O address [0x%x]\n", pcic_pci_ioaddr); break; default: pcic_pci_ioaddr = pci_conf_read(tag, PCI_MAP_REG_START) --- 148,187 ---- int i,j; u_char *p; u_long *pl; + unsigned long bcr; /* to set 6832 interrupts -- tvf*/ switch (pcic_pci_id) { case PCI_DEVICE_ID_PCIC_TI1130_CARDBUS: pcic_pci_ioaddr = pci_conf_read(tag, CARDBUS_LEGACY_16BIT_IOADDR) & ~PCI_MAP_IO; printf("CardBus: Legacy PC-card 16bit I/O address [0x%x]\n", pcic_pci_ioaddr); break; + case PCI_DEVICE_ID_PCIC_CLPD6832_CARDBUS: + /* Set up the 6832 at the compatibility address -- tvf */ + pcic_pci_ioaddr = 0x000003e0; + /* This is the first I/O window, which we'll use */ + + pci_conf_write(tag,PD6832_IO_BASE0, pcic_pci_ioaddr | 1); + pci_conf_write(tag,PD6832_IO_LIMIT0, (pcic_pci_ioaddr + 0x4) | 1); + /* This deactivates the second */ + + pci_conf_write(tag,PD6832_IO_BASE1, (pcic_pci_ioaddr +0x20) | 1); + pci_conf_write(tag,PD6832_IO_LIMIT1, (pcic_pci_ioaddr + 0x4) | 1 ); + + /* Map the chip into pci port space (pci_map_port properly + initializes bridges) */ + pci_map_port(tag,PD6832_IO_BASE0,&pcic_pci_ioaddr); + + /* put the 6832 into legacy mode */ + + pci_conf_write(tag,CARDBUS_LEGACY_16BIT_IOADDR, pcic_pci_ioaddr | 1); + printf("CardBus: Legacy PC-card 16bit I/O address [0x%x]\n", + pcic_pci_ioaddr); + break; + + default: pcic_pci_ioaddr = pci_conf_read(tag, PCI_MAP_REG_START) *************** *** 159,164 **** --- 193,226 ---- case PCI_DEVICE_ID_PCIC_CLPD6729: case PCI_DEVICE_ID_PCIC_O2MICRO: pci_conf_write(tag, PCI_COMMAND_STATUS_REG, 0x00ff00ff); + break; + case PCI_DEVICE_ID_PCIC_CLPD6832_CARDBUS: + + /* Configure for IO mapping ---tvf */ + pci_conf_write(tag, PCI_COMMAND_STATUS_REG, 0x000000045); + + /* Assign the socket to this register set (attach gets called + per slot */ + pci_conf_write(tag, PD6832_SOCKET,unit); + + /* Set up the card in/card out interrupts to come here */ + + bcr = pci_conf_read(tag,PD6832_BRIDGE_CONTROL); + bcr |= (PD6832_BCR_ISA_IRQ|PD6832_BCR_MGMT_IRQ_ENA); + pci_conf_write(tag,PD6832_BRIDGE_CONTROL,bcr); + if (!bootverbose) + break; + + /* useful for debugging */ + + printf ("PCI Config space:\n"); + for (j = 0; j < 0x98; j += 16) { + printf("%02x: ", j); + for (i = 0; i < 16; i += 4) { + printf(" %08x", pci_conf_read(tag, i+j)); + } + printf("\n"); + } break; /* CardBus Bridges */ default: *** pci/pcireg.h.orig Thu Apr 24 01:05:15 1997 --- pci/pcireg.h Mon Oct 6 14:54:00 1997 *************** *** 139,145 **** ** Mapping registers */ #define PCI_MAP_REG_START 0x10 ! #define PCI_MAP_REG_END 0x28 #define PCI_MAP_MEMORY 0x00000000 #define PCI_MAP_IO 0x00000001 --- 139,145 ---- ** Mapping registers */ #define PCI_MAP_REG_START 0x10 ! #define PCI_MAP_REG_END 0x3f #define PCI_MAP_MEMORY 0x00000000 #define PCI_MAP_IO 0x00000001
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