Date: Wed, 21 Apr 2010 01:43:50 +0000 (UTC) From: Juli Mallett <jmallett@FreeBSD.org> To: src-committers@freebsd.org, svn-src-user@freebsd.org Subject: svn commit: r206975 - user/jmallett/octeon/sys/mips/cavium Message-ID: <201004210143.o3L1hoZW008426@svn.freebsd.org>
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Author: jmallett Date: Wed Apr 21 01:43:49 2010 New Revision: 206975 URL: http://svn.freebsd.org/changeset/base/206975 Log: Move to using the SDK for more things. This is incomplete at present and only boots multi-user with a single core. Something goes amiss after the second core crashes. This also disables the RGMII driver entirely as it is going to need substantially more work to move to the SDK. Modified: user/jmallett/octeon/sys/mips/cavium/cvmx_config.h user/jmallett/octeon/sys/mips/cavium/files.octeon1 user/jmallett/octeon/sys/mips/cavium/octeon_machdep.c user/jmallett/octeon/sys/mips/cavium/octeon_mp.c user/jmallett/octeon/sys/mips/cavium/octeon_pcmap_regs.h user/jmallett/octeon/sys/mips/cavium/uart_dev_oct16550.c Modified: user/jmallett/octeon/sys/mips/cavium/cvmx_config.h ============================================================================== --- user/jmallett/octeon/sys/mips/cavium/cvmx_config.h Wed Apr 21 01:39:52 2010 (r206974) +++ user/jmallett/octeon/sys/mips/cavium/cvmx_config.h Wed Apr 21 01:43:49 2010 (r206975) @@ -1,7 +1,18 @@ #ifndef _CVMX_CONFIG_H #define _CVMX_CONFIG_H +#include <sys/types.h> +#include <sys/param.h> +#include <sys/systm.h> + +#include <vm/vm.h> +#include <vm/pmap.h> + +#include <machine/pmap.h> + #define asm __asm #define volatile __volatile +#define CVMX_DONT_INCLUDE_CONFIG + #endif /* !_CVMX_CONFIG_H */ Modified: user/jmallett/octeon/sys/mips/cavium/files.octeon1 ============================================================================== --- user/jmallett/octeon/sys/mips/cavium/files.octeon1 Wed Apr 21 01:39:52 2010 (r206974) +++ user/jmallett/octeon/sys/mips/cavium/files.octeon1 Wed Apr 21 01:43:49 2010 (r206975) @@ -2,10 +2,6 @@ # Octeon Support Files # mips/cavium/asm_octeon.S optional smp -mips/cavium/dev/rgmii/octeon_fpa.c optional rgmii -mips/cavium/dev/rgmii/octeon_ipd.c optional rgmii -mips/cavium/dev/rgmii/octeon_pko.c optional rgmii -mips/cavium/dev/rgmii/octeon_rgmx.c optional rgmii mips/cavium/obio.c optional uart mips/cavium/octeon_ebt3000_cf.c optional cf mips/cavium/octeon_machdep.c standard @@ -15,3 +11,11 @@ mips/cavium/uart_cpu_octeonusart.c opti mips/cavium/uart_dev_oct16550.c optional uart mips/mips/intr_machdep.c standard mips/mips/tick.c standard + +#mips/cavium/dev/rgmii/octeon_fpa.c optional rgmii +#mips/cavium/dev/rgmii/octeon_ipd.c optional rgmii +#mips/cavium/dev/rgmii/octeon_pko.c optional rgmii +#mips/cavium/dev/rgmii/octeon_rgmx.c optional rgmii +mips/mips/tick.c optional rgmii + +contrib/octeon-sdk/cvmx-sysinfo.c standard Modified: user/jmallett/octeon/sys/mips/cavium/octeon_machdep.c ============================================================================== --- user/jmallett/octeon/sys/mips/cavium/octeon_machdep.c Wed Apr 21 01:39:52 2010 (r206974) +++ user/jmallett/octeon/sys/mips/cavium/octeon_machdep.c Wed Apr 21 01:43:49 2010 (r206975) @@ -70,6 +70,9 @@ __FBSDID("$FreeBSD$"); #include <machine/trap.h> #include <machine/vmparam.h> +#include <contrib/octeon-sdk/cvmx.h> +#include <contrib/octeon-sdk/cvmx-interrupt.h> + #if defined(__mips_n64) #define MAX_APP_DESC_ADDR 0xffffffffafffffff #else @@ -83,8 +86,6 @@ uint64_t ciu_get_en_reg_addr_new(int cor void ciu_dump_interrutps_enabled(int core_num, int intx, int enx, int ciu_ip); static void octeon_boot_params_init(register_t ptr); -static uint64_t ciu_get_intr_sum_reg_addr(int core_num, int intx, int enx); -static uint64_t ciu_get_intr_en_reg_addr(int core_num, int intx, int enx); void platform_cpu_init() @@ -98,7 +99,7 @@ platform_cpu_init() void platform_reset(void) { - oct_write64(OCTEON_CIU_SOFT_RST, 1); + oct_write64(CVMX_CIU_SOFT_RST, 1); } void @@ -195,23 +196,6 @@ octeon_debug_symbol(void) { } -void -octeon_ciu_stop_gtimer(int timer) -{ - oct_write64(OCTEON_CIU_GENTIMER_ADDR(timer), 0ll); -} - -void -octeon_ciu_start_gtimer(int timer, u_int one_shot, uint64_t time_cycles) -{ - octeon_ciu_gentimer gentimer; - - gentimer.word64 = 0; - gentimer.bits.one_shot = one_shot; - gentimer.bits.len = time_cycles - 1; - oct_write64(OCTEON_CIU_GENTIMER_ADDR(timer), gentimer.word64); -} - /* * octeon_ciu_reset * @@ -220,294 +204,11 @@ octeon_ciu_start_gtimer(int timer, u_int void octeon_ciu_reset(void) { - - octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_0); - octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_1); - octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_2); - octeon_ciu_stop_gtimer(CIU_GENTIMER_NUM_3); - - ciu_disable_intr(CIU_THIS_CORE, CIU_INT_0, CIU_EN_0); - ciu_disable_intr(CIU_THIS_CORE, CIU_INT_0, CIU_EN_1); - ciu_disable_intr(CIU_THIS_CORE, CIU_INT_1, CIU_EN_0); - ciu_disable_intr(CIU_THIS_CORE, CIU_INT_1, CIU_EN_1); - - ciu_clear_int_summary(CIU_THIS_CORE, CIU_INT_0, CIU_EN_0, 0ll); - ciu_clear_int_summary(CIU_THIS_CORE, CIU_INT_1, CIU_EN_0, 0ll); - ciu_clear_int_summary(CIU_THIS_CORE, CIU_INT_1, CIU_EN_1, 0ll); -} - -/* - * mips_disable_interrupt_controllers - * - * Disable interrupts in the CPU controller - */ -void -mips_disable_interrupt_controls(void) -{ - /* - * Disable interrupts in CIU. - */ - octeon_ciu_reset(); -} - -/* - * ciu_get_intr_sum_reg_addr - */ -static uint64_t -ciu_get_intr_sum_reg_addr(int core_num, int intx, int enx) -{ - uint64_t ciu_intr_sum_reg_addr; - - if (enx == CIU_EN_0) - ciu_intr_sum_reg_addr = OCTEON_CIU_SUMMARY_BASE_ADDR + - (core_num * 0x10) + (intx * 0x8); - else - ciu_intr_sum_reg_addr = OCTEON_CIU_SUMMARY_INT1_ADDR; - - return (ciu_intr_sum_reg_addr); -} - - -/* - * ciu_get_intr_en_reg_addr - */ -static uint64_t -ciu_get_intr_en_reg_addr(int core_num, int intx, int enx) -{ - uint64_t ciu_intr_reg_addr; - - ciu_intr_reg_addr = OCTEON_CIU_ENABLE_BASE_ADDR + - ((enx == 0) ? 0x0 : 0x8) + (intx * 0x10) + (core_num * 0x20); - return (ciu_intr_reg_addr); -} - - - - -/* - * ciu_get_intr_reg_addr - * - * 200 ---int0,en0 ip2 - * 208 ---int0,en1 ip2 ----> this is wrong... this is watchdog - * - * 210 ---int0,en0 ip3 -- - * 218 ---int0,en1 ip3 ----> same here.. .this is watchdog... right? - * - * 220 ---int1,en0 ip2 - * 228 ---int1,en1 ip2 - * 230 ---int1,en0 ip3 -- - * 238 ---int1,en1 ip3 - * - */ -uint64_t -ciu_get_en_reg_addr_new(int corenum, int intx, int enx, int ciu_ip) -{ - uint64_t ciu_intr_reg_addr = OCTEON_CIU_ENABLE_BASE_ADDR; - - /* XXX kasserts? */ - if (enx < CIU_EN_0 || enx > CIU_EN_1) { - printf("%s: invalid enx value %d, should be %d or %d\n", - __func__, enx, CIU_EN_0, CIU_EN_1); - return 0; - } - if (intx < CIU_INT_0 || intx > CIU_INT_1) { - printf("%s: invalid intx value %d, should be %d or %d\n", - __func__, enx, CIU_INT_0, CIU_INT_1); - return 0; - } - if (ciu_ip < CIU_MIPS_IP2 || ciu_ip > CIU_MIPS_IP3) { - printf("%s: invalid ciu_ip value %d, should be %d or %d\n", - __func__, ciu_ip, CIU_MIPS_IP2, CIU_MIPS_IP3); - return 0; - } - - ciu_intr_reg_addr += (enx * 0x8); - ciu_intr_reg_addr += (ciu_ip * 0x10); - ciu_intr_reg_addr += (intx * 0x20); - return (ciu_intr_reg_addr); -} - -/* - * ciu_get_int_summary - */ -uint64_t -ciu_get_int_summary(int core_num, int intx, int enx) -{ - uint64_t ciu_intr_sum_reg_addr; - - if (core_num == CIU_THIS_CORE) - core_num = octeon_get_core_num(); - ciu_intr_sum_reg_addr = ciu_get_intr_sum_reg_addr(core_num, intx, enx); - return (oct_read64(ciu_intr_sum_reg_addr)); -} - -//#define DEBUG_CIU 1 - -#ifdef DEBUG_CIU -#define DEBUG_CIU_SUM 1 -#define DEBUG_CIU_EN 1 -#endif - - -/* - * ciu_clear_int_summary - */ -void -ciu_clear_int_summary(int core_num, int intx, int enx, uint64_t write_bits) -{ - uint32_t cpu_status_bits; - uint64_t ciu_intr_sum_reg_addr; - -//#define DEBUG_CIU_SUM 1 - -#ifdef DEBUG_CIU_SUM - uint64_t ciu_intr_sum_bits; -#endif - - - if (core_num == CIU_THIS_CORE) { - core_num = octeon_get_core_num(); - } - -#ifdef DEBUG_CIU_SUM - printf(" CIU: core %u clear sum IntX %u Enx %u Bits: 0x%llX\n", - core_num, intx, enx, write_bits); -#endif - - cpu_status_bits = intr_disable(); - - ciu_intr_sum_reg_addr = ciu_get_intr_sum_reg_addr(core_num, intx, enx); - -#ifdef DEBUG_CIU_SUM - ciu_intr_sum_bits = oct_read64(ciu_intr_sum_reg_addr); /* unneeded dummy read */ - printf(" CIU: status: 0x%X reg_addr: 0x%llX Val: 0x%llX -> 0x%llX", - cpu_status_bits, ciu_intr_sum_reg_addr, ciu_intr_sum_bits, - ciu_intr_sum_bits | write_bits); -#endif - - oct_write64(ciu_intr_sum_reg_addr, write_bits); - oct_read64(OCTEON_MIO_BOOT_BIST_STAT); /* Bus Barrier */ - -#ifdef DEBUG_CIU_SUM - printf(" Readback: 0x%llX\n\n ", (uint64_t) oct_read64(ciu_intr_sum_reg_addr)); -#endif - - intr_restore(cpu_status_bits); -} - -/* - * ciu_disable_intr - */ -void -ciu_disable_intr(int core_num, int intx, int enx) -{ - uint32_t cpu_status_bits; - uint64_t ciu_intr_reg_addr; - - if (core_num == CIU_THIS_CORE) - core_num = octeon_get_core_num(); - - cpu_status_bits = intr_disable(); - - ciu_intr_reg_addr = ciu_get_intr_en_reg_addr(core_num, intx, enx); - - oct_read64(ciu_intr_reg_addr); /* Dummy read */ - - oct_write64(ciu_intr_reg_addr, 0LL); - oct_read64(OCTEON_MIO_BOOT_BIST_STAT); /* Bus Barrier */ - - intr_restore(cpu_status_bits); -} - -void -ciu_dump_interrutps_enabled(int core_num, int intx, int enx, int ciu_ip) -{ - - uint64_t ciu_intr_reg_addr; - uint64_t ciu_intr_bits; - - if (core_num == CIU_THIS_CORE) { - core_num = octeon_get_core_num(); - } - -#ifndef OCTEON_SMP_1 - ciu_intr_reg_addr = ciu_get_intr_en_reg_addr(core_num, intx, enx); -#else - ciu_intr_reg_addr = ciu_get_en_reg_addr_new(core_num, intx, enx, ciu_ip); -#endif - - if (!ciu_intr_reg_addr) { - printf("Bad call to %s\n", __func__); - while(1); - return; - } - - ciu_intr_bits = oct_read64(ciu_intr_reg_addr); - printf(" CIU core %d int: %d en: %d ip: %d Add: %#llx enabled: %#llx SR: %x\n", - core_num, intx, enx, ciu_ip, (unsigned long long)ciu_intr_reg_addr, - (unsigned long long)ciu_intr_bits, mips_rd_status()); -} - - -/* - * ciu_enable_interrupts - */ -void ciu_enable_interrupts(int core_num, int intx, int enx, - uint64_t set_these_interrupt_bits, int ciu_ip) -{ - uint32_t cpu_status_bits; - uint64_t ciu_intr_reg_addr; - uint64_t ciu_intr_bits; - - if (core_num == CIU_THIS_CORE) - core_num = octeon_get_core_num(); - -//#define DEBUG_CIU_EN 1 - -#ifdef DEBUG_CIU_EN - printf(" CIU: core %u enabling Intx %u Enx %u IP %d Bits: 0x%llX\n", - core_num, intx, enx, ciu_ip, set_these_interrupt_bits); -#endif - - cpu_status_bits = intr_disable(); - -#ifndef OCTEON_SMP_1 - ciu_intr_reg_addr = ciu_get_intr_en_reg_addr(core_num, intx, enx); -#else - ciu_intr_reg_addr = ciu_get_en_reg_addr_new(core_num, intx, enx, ciu_ip); -#endif - - if (!ciu_intr_reg_addr) { - printf("Bad call to %s\n", __func__); - while(1); - return; /* XXX */ - } - - ciu_intr_bits = oct_read64(ciu_intr_reg_addr); - -#ifdef DEBUG_CIU_EN - printf(" CIU: status: 0x%X reg_addr: 0x%llX Val: 0x%llX -> 0x%llX", - cpu_status_bits, ciu_intr_reg_addr, ciu_intr_bits, ciu_intr_bits | set_these_interrupt_bits); -#endif - ciu_intr_bits |= set_these_interrupt_bits; - oct_write64(ciu_intr_reg_addr, ciu_intr_bits); -#ifdef SMP - mips_wbflush(); -#endif - oct_read64(OCTEON_MIO_BOOT_BIST_STAT); /* Bus Barrier */ - -#ifdef DEBUG_CIU_EN - printf(" Readback: 0x%llX\n\n ", - (uint64_t)oct_read64(ciu_intr_reg_addr)); -#endif - - intr_restore(cpu_status_bits); -} - -unsigned long -octeon_get_clock_rate(void) -{ - return octeon_cpu_clock; + /* Disable all CIU interrupts by default */ + cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0); + cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0); + cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0); + cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0); } static void @@ -601,15 +302,15 @@ platform_start(__register_t a0, __regist if (boothowto & RB_KDB) kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); #endif - platform_counter_freq = octeon_get_clock_rate(); + platform_counter_freq = cvmx_sysinfo_get()->cpu_clock_hz; mips_timer_init_params(platform_counter_freq, 0); #ifdef SMP /* * Clear any pending IPIs and enable the IPI interrupt. */ - oct_write64(OCTEON_CIU_MBOX_CLRX(0), 0xffffffff); - ciu_enable_interrupts(0, CIU_INT_1, CIU_EN_0, OCTEON_CIU_ENABLE_MBOX_INTR, CIU_MIPS_IP3); + oct_write64(CVMX_CIU_MBOX_CLRX(0), 0xffffffff); + cvmx_interrupt_unmask_irq(CVMX_IRQ_MBOX0); #endif } @@ -642,7 +343,6 @@ platform_start(__register_t a0, __regist #define OCTEON_ARGV_MAX_ARGS (64) #define OCTOEN_SERIAL_LEN 20 - typedef struct { /* Start of block referenced by assembly code - do not change! */ uint32_t desc_version; @@ -680,43 +380,10 @@ typedef struct { uint64_t cvmx_desc_vaddr; } octeon_boot_descriptor_t; - -typedef struct { - uint32_t major_version; - uint32_t minor_version; - - uint64_t stack_top; - uint64_t heap_base; - uint64_t heap_end; - uint64_t desc_vaddr; - - uint32_t exception_base_addr; - uint32_t stack_size; - uint32_t flags; - uint32_t core_mask; - uint32_t dram_size; /**< DRAM size in megabyes */ - uint32_t phy_mem_desc_addr; /**< physical address of free memory descriptor block*/ - uint32_t debugger_flags_base_addr; /**< used to pass flags from app to debugger */ - uint32_t eclock_hz; /**< CPU clock speed, in hz */ - uint32_t dclock_hz; /**< DRAM clock speed, in hz */ - uint32_t spi_clock_hz; /**< SPI4 clock in hz */ - uint16_t board_type; - uint8_t board_rev_major; - uint8_t board_rev_minor; - uint16_t chip_type; - uint8_t chip_rev_major; - uint8_t chip_rev_minor; - char board_serial_number[OCTOEN_SERIAL_LEN]; - uint8_t mac_addr_base[6]; - uint8_t mac_addr_count; -} cvmx_bootinfo_t; - -uint32_t octeon_cpu_clock; uint64_t octeon_dram; -uint32_t octeon_bd_ver = 0, octeon_cvmx_bd_ver = 0, octeon_board_rev_major, octeon_board_rev_minor, octeon_board_type; +static uint32_t octeon_bd_ver = 0, octeon_cvmx_bd_ver = 0; uint8_t octeon_mac_addr[6] = { 0 }; int octeon_core_mask, octeon_mac_addr_count; -int octeon_chip_rev_major = 0, octeon_chip_rev_minor = 0, octeon_chip_type = 0; static octeon_boot_descriptor_t *app_desc_ptr; static cvmx_bootinfo_t *cvmx_desc_ptr; @@ -735,7 +402,7 @@ static cvmx_bootinfo_t *cvmx_desc_ptr; int octeon_board_real(void) { - switch (octeon_board_type) { + switch (cvmx_sysinfo_get()->board_type) { case OCTEON_BOARD_TYPE_NONE: case OCTEON_BOARD_TYPE_SIM: return 0; @@ -748,7 +415,7 @@ octeon_board_real(void) */ return 1; default: - if (octeon_board_rev_major == 0) + if (cvmx_sysinfo_get()->board_rev_major == 0) return 0; return 1; } @@ -759,15 +426,15 @@ octeon_process_app_desc_ver_unknown(void { printf(" Unknown Boot-Descriptor: Using Defaults\n"); - octeon_cpu_clock = OCTEON_CLOCK_DEFAULT; octeon_dram = OCTEON_DRAM_DEFAULT; - octeon_board_rev_major = octeon_board_rev_minor = octeon_board_type = 0; octeon_core_mask = 1; - octeon_chip_type = octeon_chip_rev_major = octeon_chip_rev_minor = 0; octeon_mac_addr[0] = 0x00; octeon_mac_addr[1] = 0x0f; octeon_mac_addr[2] = 0xb7; octeon_mac_addr[3] = 0x10; octeon_mac_addr[4] = 0x09; octeon_mac_addr[5] = 0x06; octeon_mac_addr_count = 1; + + cvmx_sysinfo_minimal_initialize(NULL, CVMX_BOARD_TYPE_NULL, + 0, 0, OCTEON_CLOCK_DEFAULT); } static int @@ -792,13 +459,6 @@ octeon_process_app_desc_ver_6(void) } octeon_core_mask = cvmx_desc_ptr->core_mask; - octeon_cpu_clock = cvmx_desc_ptr->eclock_hz; - octeon_board_type = cvmx_desc_ptr->board_type; - octeon_board_rev_major = cvmx_desc_ptr->board_rev_major; - octeon_board_rev_minor = cvmx_desc_ptr->board_rev_minor; - octeon_chip_type = cvmx_desc_ptr->chip_type; - octeon_chip_rev_major = cvmx_desc_ptr->chip_rev_major; - octeon_chip_rev_minor = cvmx_desc_ptr->chip_rev_minor; octeon_mac_addr[0] = cvmx_desc_ptr->mac_addr_base[0]; octeon_mac_addr[1] = cvmx_desc_ptr->mac_addr_base[1]; octeon_mac_addr[2] = cvmx_desc_ptr->mac_addr_base[2]; @@ -811,6 +471,15 @@ octeon_process_app_desc_ver_6(void) octeon_dram = (uint64_t)app_desc_ptr->dram_size; else octeon_dram = (uint64_t)app_desc_ptr->dram_size << 20; + + /* + * XXX + * We could pass in phy_mem_desc_ptr, but why bother? + */ + cvmx_sysinfo_minimal_initialize(NULL, cvmx_desc_ptr->board_type, + cvmx_desc_ptr->board_rev_major, + cvmx_desc_ptr->board_rev_minor, + cvmx_desc_ptr->eclock_hz); return 0; } @@ -831,13 +500,19 @@ octeon_boot_params_init(register_t ptr) octeon_process_app_desc_ver_unknown(); printf("Boot Descriptor Ver: %u -> %u/%u", - octeon_bd_ver, octeon_cvmx_bd_ver/100, octeon_cvmx_bd_ver%100); - printf(" CPU clock: %uMHz Core Mask: %#x\n", octeon_cpu_clock/1000000, octeon_core_mask); + octeon_bd_ver, octeon_cvmx_bd_ver / 100, + octeon_cvmx_bd_ver % 100); + printf(" CPU clock: %uMHz Core Mask: %#x\n", + cvmx_sysinfo_get()->cpu_clock_hz / 1000000, octeon_core_mask); printf(" Dram: %u MB", (uint32_t)(octeon_dram >> 20)); printf(" Board Type: %u Revision: %u/%u\n", - octeon_board_type, octeon_board_rev_major, octeon_board_rev_minor); + cvmx_sysinfo_get()->board_type, + cvmx_sysinfo_get()->board_rev_major, + cvmx_sysinfo_get()->board_rev_minor); +#if 0 printf(" Octeon Chip: %u Rev %u/%u", octeon_chip_type, octeon_chip_rev_major, octeon_chip_rev_minor); +#endif printf(" Mac Address %02X.%02X.%02X.%02X.%02X.%02X (%d)\n", octeon_mac_addr[0], octeon_mac_addr[1], octeon_mac_addr[2], Modified: user/jmallett/octeon/sys/mips/cavium/octeon_mp.c ============================================================================== --- user/jmallett/octeon/sys/mips/cavium/octeon_mp.c Wed Apr 21 01:39:52 2010 (r206974) +++ user/jmallett/octeon/sys/mips/cavium/octeon_mp.c Wed Apr 21 01:43:49 2010 (r206975) @@ -38,12 +38,15 @@ __FBSDID("$FreeBSD$"); #include <mips/cavium/octeon_pcmap_regs.h> +#include <contrib/octeon-sdk/cvmx.h> +#include <contrib/octeon-sdk/cvmx-interrupt.h> + unsigned octeon_ap_boot = ~0; void platform_ipi_send(int cpuid) { - oct_write64(OCTEON_CIU_MBOX_SETX(cpuid), 1); + oct_write64(CVMX_CIU_MBOX_SETX(cpuid), 1); mips_wbflush(); } @@ -52,9 +55,9 @@ platform_ipi_clear(void) { uint64_t action; - action = oct_read64(OCTEON_CIU_MBOX_CLRX(PCPU_GET(cpuid))); + action = oct_read64(CVMX_CIU_MBOX_CLRX(PCPU_GET(cpuid))); KASSERT(action == 1, ("unexpected IPIs: %#jx", (uintmax_t)action)); - oct_write64(OCTEON_CIU_MBOX_CLRX(PCPU_GET(cpuid)), action); + oct_write64(CVMX_CIU_MBOX_CLRX(PCPU_GET(cpuid)), action); } int @@ -76,8 +79,8 @@ platform_init_ap(int cpuid) */ octeon_ciu_reset(); - oct_write64(OCTEON_CIU_MBOX_CLRX(cpuid), 0xffffffff); - ciu_enable_interrupts(cpuid, CIU_INT_1, CIU_EN_0, OCTEON_CIU_ENABLE_MBOX_INTR, CIU_MIPS_IP3); + oct_write64(CVMX_CIU_MBOX_CLRX(cpuid), 0xffffffff); + cvmx_interrupt_unmask_irq(CVMX_IRQ_MBOX0); mips_wbflush(); } Modified: user/jmallett/octeon/sys/mips/cavium/octeon_pcmap_regs.h ============================================================================== --- user/jmallett/octeon/sys/mips/cavium/octeon_pcmap_regs.h Wed Apr 21 01:39:52 2010 (r206974) +++ user/jmallett/octeon/sys/mips/cavium/octeon_pcmap_regs.h Wed Apr 21 01:43:49 2010 (r206975) @@ -48,20 +48,12 @@ #include "opt_cputype.h" -#define OCTEON_CACHE_LINE_SIZE 0x80 /* 128 bytes cache line size */ -#define IS_OCTEON_ALIGNED(p) (!((u_long)(p) & 0x7f)) -#define OCTEON_ALIGN(p) (((u_long)(p) + ((OCTEON_CACHE_LINE_SIZE) - 1)) & ~((OCTEON_CACHE_LINE_SIZE) - 1)) - #ifndef LOCORE /* * Utility inlines & macros */ -/* turn the variable name into a string */ -#define OCTEON_TMP_STR(x) OCTEON_TMP_STR2(x) -#define OCTEON_TMP_STR2(x) #x - #if defined(__mips_n64) #define oct_write64(a, v) (*(volatile uint64_t *)(a) = (uint64_t)(v)) #define oct_write8_x8(a, v) (*(volatile uint8_t *)(a) = (uint8_t)(v)) @@ -359,19 +351,6 @@ static inline mipsx_addr_size octeon_ptr #define OCTEON_IO_SEG OCTEON_MIPS_SPACE_XKPHYS - -#define OCTEON_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add)) - -#define OCTEON_ADD_IO_SEG(add) OCTEON_ADD_SEG(OCTEON_IO_SEG, (add)) -#define OCTEON_ADDR_DID(did) (OCTEON_ADDR_DIDSPACE(did) << 40) -#define OCTEON_ADDR_DIDSPACE(did) (((OCTEON_IO_SEG) << 22) | ((1ULL) << 8) | (did)) -#define OCTEON_ADDR_FULL_DID(did,subdid) (((did) << 3) | (subdid)) - - -#define OCTEON_CIU_PP_RST OCTEON_ADD_IO_SEG(0x0001070000000700ull) -#define OCTEON_CIU_SOFT_RST OCTEON_ADD_IO_SEG(0x0001070000000740ull) -#define OCTEON_OCTEON_DID_TAG 12ULL - /* * octeon_addr_t */ @@ -511,12 +490,6 @@ static inline uint32_t octeon_get_chipid } -static inline unsigned int get_coremask (void) -{ - return(~(oct_read64(OCTEON_CIU_PP_RST)) & 0xffff); -} - - static inline uint32_t octeon_get_core_num (void) { @@ -577,37 +550,12 @@ extern void octeon_reset(void); extern void octeon_led_write_char0(char val); extern void octeon_led_run_wheel(int *pos, int led_position); extern void octeon_debug_symbol(void); -extern void mips_disable_interrupt_controls(void); -extern uint32_t octeon_cpu_clock; extern uint64_t octeon_dram; -extern uint32_t octeon_bd_ver, octeon_board_rev_major, octeon_board_rev_minor, octeon_board_type; extern uint8_t octeon_mac_addr[6]; -extern int octeon_core_mask, octeon_mac_addr_count, octeon_chip_rev_major, octeon_chip_rev_minor, octeon_chip_type; -extern void bzero_64(void *str, size_t len); -extern void bzero_32(void *str, size_t len); -extern void bzero_16(void *str, size_t len); -extern void bzero_old(void *str, size_t len); +extern int octeon_core_mask, octeon_mac_addr_count; extern void octeon_ciu_reset(void); -extern void ciu_disable_intr(int core_num, int intx, int enx); -extern void ciu_enable_interrupts (int core_num, int intx, int enx, uint64_t set_these_interrupt_bits, int ciu_ip); -extern void ciu_clear_int_summary(int core_num, int intx, int enx, uint64_t write_bits); -extern uint64_t ciu_get_int_summary(int core_num, int intx, int enx); -extern void octeon_ciu_start_gtimer(int timer, u_int one_shot, uint64_t time_cycles); -extern void octeon_ciu_stop_gtimer(int timer); extern int octeon_board_real(void); extern unsigned long octeon_get_clock_rate(void); - -typedef union { - uint64_t word64; - struct { - uint64_t reserved : 27; /* Not used */ - uint64_t one_shot : 1; /* Oneshot ? */ - uint64_t len : 36; /* len of timer in clock cycles - 1 */ - } bits; -} octeon_ciu_gentimer; - - - #endif /* LOCORE */ @@ -645,96 +593,6 @@ typedef union { #define OCTEON_FPA_QUEUES 8 /* - * Octeon FPA I/O Registers - */ -#define OCTEON_FPA_CTL_STATUS 0x8001180028000050ull -#define OCTEON_FPA_FPF_SIZE 0x8001180028000058ull -#define OCTEON_FPA_FPF_MARKS 0x8001180028000000ull -#define OCTEON_FPA_INT_SUMMARY 0x8001180028000040ull -#define OCTEON_FPA_INT_ENABLE 0x8001180028000048ull -#define OCTEON_FPA_QUEUE_AVAILABLE 0x8001180028000098ull -#define OCTEON_FPA_PAGE_INDEX 0x80011800280000f0ull - -/* - * Octeon PKO Unit - */ -#define OCTEON_PKO_REG_FLAGS 0x8001180050000000ull -#define OCTEON_PKO_REG_READ_IDX 0x8001180050000008ull -#define OCTEON_PKO_CMD_BUF 0x8001180050000010ull -#define OCTEON_PKO_GMX_PORT_MODE 0x8001180050000018ull -#define OCTEON_PKO_REG_CRC_ENABLE 0x8001180050000020ull -#define OCTEON_PKO_QUEUE_MODE 0x8001180050000048ull -#define OCTEON_PKO_MEM_QUEUE_PTRS 0x8001180050001000ull -#define OCTEON_PKO_MEM_COUNT0 0x8001180050001080ull -#define OCTEON_PKO_MEM_COUNT1 0x8001180050001088ull -#define OCTEON_PKO_MEM_DEBUG0 0x8001180050001100ull -#define OCTEON_PKO_MEM_DEBUG1 0x8001180050001108ull -#define OCTEON_PKO_MEM_DEBUG2 0x8001180050001110ull -#define OCTEON_PKO_MEM_DEBUG3 0x8001180050001118ull -#define OCTEON_PKO_MEM_DEBUG4 0x8001180050001120ull -#define OCTEON_PKO_MEM_DEBUG5 0x8001180050001128ull -#define OCTEON_PKO_MEM_DEBUG6 0x8001180050001130ull -#define OCTEON_PKO_MEM_DEBUG7 0x8001180050001138ull -#define OCTEON_PKO_MEM_DEBUG8 0x8001180050001140ull -#define OCTEON_PKO_MEM_DEBUG9 0x8001180050001148ull - - -/* - * Octeon IPD Unit - */ -#define OCTEON_IPD_1ST_MBUFF_SKIP 0x80014F0000000000ull -#define OCTEON_IPD_NOT_1ST_MBUFF_SKIP 0x80014F0000000008ull -#define OCTEON_IPD_PACKET_MBUFF_SIZE 0x80014F0000000010ull -#define OCTEON_IPD_1ST_NEXT_PTR_BACK 0x80014F0000000150ull -#define OCTEON_IPD_2ND_NEXT_PTR_BACK 0x80014F0000000158ull -#define OCTEON_IPD_WQE_FPA_QUEUE 0x80014F0000000020ull -#define OCTEON_IPD_CTL_STATUS 0x80014F0000000018ull -#define OCTEON_IPD_QOSX_RED_MARKS(queue) (0x80014F0000000178ull + ((queue) * 8)) -#define OCTEON_IPD_RED_Q_PARAM(queue) (0x80014F00000002E0ull + ((queue) * 8)) -#define OCTEON_IPD_PORT_BP_PAGE_COUNT(port) (0x80014F0000000028ull + ((port) * 8)) -#define OCTEON_IPD_BP_PORT_RED_END 0x80014F0000000328ull -#define OCTEON_IPD_RED_PORT_ENABLE 0x80014F00000002D8ull - -/* - * Octeon CIU Unit - */ -#define OCTEON_CIU_ENABLE_BASE_ADDR 0x8001070000000200ull -#define OCTEON_CIU_SUMMARY_BASE_ADDR 0x8001070000000000ull -#define OCTEON_CIU_SUMMARY_INT1_ADDR 0x8001070000000108ull - -#define OCTEON_CIU_MBOX_SETX(offset) (0x8001070000000600ull+((offset)*8)) -#define OCTEON_CIU_MBOX_CLRX(offset) (0x8001070000000680ull+((offset)*8)) -#define OCTEON_CIU_ENABLE_MBOX_INTR 0x0000000300000000ull /* bits 32, 33 */ - -#define CIU_MIPS_IP2 0 -#define CIU_MIPS_IP3 1 - -#define CIU_INT_0 CIU_MIPS_IP2 -#define CIU_INT_1 CIU_MIPS_IP3 - -#define CIU_EN_0 0 -#define CIU_EN_1 1 - -#define CIU_THIS_CORE -1 - -#define CIU_UART_BITS_UART0 (0x1ull << 34) // Bit 34 -#define CIU_UART_BITS_UART1 (0x1ull << 35) // Bit 35 -#define CIU_GENTIMER_BITS_ENABLE(timer) (0x1ull << (52 + (timer))) // Bit 52..55 - -#define CIU_GENTIMER_NUM_0 0 -#define CIU_GENTIMER_NUM_1 1 -#define CIU_GENTIMER_NUM_2 2 -#define CIU_GENTIMER_NUM_3 3 -#define OCTEON_GENTIMER_ONESHOT 1 -#define OCTEON_GENTIMER_PERIODIC 0 - -#define OCTEON_CIU_GENTIMER_ADDR(timer) (0x8001070000000480ull + ((timer) * 0x8)) - - -#define OCTEON_GENTIMER_LEN_1MS (0x7a120ull) /* Back of envelope. 500Mhz Octeon */ // FIXME IF WRONG -#define OCTEON_GENTIMER_LEN_1SEC ((OCTEON_GENTIMER_LEN_1MS) * 1000) - -/* * Physical Memory Banks */ /* 1st BANK */ Modified: user/jmallett/octeon/sys/mips/cavium/uart_dev_oct16550.c ============================================================================== --- user/jmallett/octeon/sys/mips/cavium/uart_dev_oct16550.c Wed Apr 21 01:39:52 2010 (r206974) +++ user/jmallett/octeon/sys/mips/cavium/uart_dev_oct16550.c Wed Apr 21 01:43:49 2010 (r206975) @@ -72,6 +72,9 @@ __FBSDID("$FreeBSD$"); #include <mips/cavium/octeon_pcmap_regs.h> +#include <contrib/octeon-sdk/cvmx.h> +#include <contrib/octeon-sdk/cvmx-interrupt.h> + #include "uart_if.h" /* @@ -462,8 +465,16 @@ oct16550_bus_attach (struct uart_softc * /* * Enable the interrupt in CIU. // UART-x2 @ IP2 */ - ciu_enable_interrupts(0, CIU_INT_0, CIU_EN_0, - (!unit) ? CIU_UART_BITS_UART0 : CIU_UART_BITS_UART1, CIU_MIPS_IP2); + switch (unit) { + case 0: + cvmx_interrupt_unmask_irq(CVMX_IRQ_UART0); + break; + case 1: + cvmx_interrupt_unmask_irq(CVMX_IRQ_UART1); + break; + default: + panic("%s: invalid UART %d", __func__, unit); + } return (0); } @@ -671,7 +682,7 @@ oct16550_bus_probe (struct uart_softc *s int error; bas = &sc->sc_bas; - bas->rclk = uart_oct16550_class.uc_rclk = octeon_cpu_clock; + bas->rclk = uart_oct16550_class.uc_rclk = cvmx_sysinfo_get()->cpu_clock_hz; error = oct16550_probe(bas); if (error) {
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