Date: Mon, 27 Sep 2010 20:35:40 +0000 (UTC) From: Juli Mallett <jmallett@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r213230 - head/sys/mips/cavium Message-ID: <201009272035.o8RKZeQi049220@svn.freebsd.org>
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Author: jmallett Date: Mon Sep 27 20:35:40 2010 New Revision: 213230 URL: http://svn.freebsd.org/changeset/base/213230 Log: Give devices lots of time to settle around programming BARs and command registers. Without this, the settings do not seem to stick for Atheros NICs in the PCI slot of the Lanner MR-320. Modified: head/sys/mips/cavium/octopci.c Modified: head/sys/mips/cavium/octopci.c ============================================================================== --- head/sys/mips/cavium/octopci.c Mon Sep 27 20:31:03 2010 (r213229) +++ head/sys/mips/cavium/octopci.c Mon Sep 27 20:35:40 2010 (r213230) @@ -659,6 +659,8 @@ octopci_init_device(device_t dev, unsign command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); octopci_write_config(dev, b, s, f, PCIR_COMMAND, command, 1); + DELAY(10000); + /* Program BARs. */ switch (hdrtype & PCIM_HDRTYPE) { case PCIM_HDRTYPE_NORMAL: @@ -685,6 +687,8 @@ octopci_init_device(device_t dev, unsign /* Enable whatever facilities the BARs require. */ octopci_write_config(dev, b, s, f, PCIR_COMMAND, command, 1); + DELAY(10000); + /* * Set cache line size. On Octeon it should be 128 bytes, * but according to Linux some Intel bridges have trouble
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