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Date:      Sat, 11 Jul 1998 08:41:51 +1000 (EST)
From:      peter.jeremyp@alcatel.com.au
To:        FreeBSD-gnats-submit@FreeBSD.ORG
Subject:   kern/7242: Clarification of comments in RTC header
Message-ID:  <199807102241.IAA15123@vk2pj.alcatel.com.au>

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>Number:         7242
>Category:       kern
>Synopsis:       Clarification of comments in RTC header
>Confidential:   no
>Severity:       non-critical
>Priority:       low
>Responsible:    freebsd-bugs
>State:          open
>Quarter:
>Keywords:
>Date-Required:
>Class:          change-request
>Submitter-Id:   current-users
>Arrival-Date:   Fri Jul 10 15:50:02 PDT 1998
>Last-Modified:
>Originator:     Peter Jeremy
>Organization:
>Release:        FreeBSD 2.2.5-RELEASE i386
>Environment:

Any FreeBSD 2.x (and maybe 3.x)

>Description:

The comments in sys/i386/isa/rtc.h are less clear than they could be.
Adding the following reduces the requirement to refer to the MC146818
data sheet to determine the code behaviour.

>How-To-Repeat:

Look at the source and patch below.

>Fix:
	
The following is a patch to 2.2.5-RELEASE or 2.2.6-RELEASE which will
clarify a number of comments.

diff -ur 2.2.6/sys/i386/isa/rtc.h 2.2.5/sys/i386/isa/rtc.h
--- 2.2.6/sys/i386/isa/rtc.h	Tue Oct 10 01:00:39 1995
+++ 2.2.5/sys/i386/isa/rtc.h	Sat Jan 17 19:26:14 1998
@@ -40,14 +40,8 @@
 #ifndef _I386_ISA_RTC_H_
 #define _I386_ISA_RTC_H_ 1
 
 /*
- * RTC Register locations
+ * MC146818 RTC Register locations
  */
 
 #define RTC_SEC		0x00	/* seconds */
@@ -57,8 +57,9 @@
 
 #define RTC_STATUSA	0x0a	/* status register A */
 #define  RTCSA_TUP	 0x80	/* time update, don't look now */
+#define  RTCSA_RESET	 0x70	/* reset divider */
 #define  RTCSA_DIVIDER   0x20   /* divider correct for 32768 Hz */
-#define  RTCSA_8192      0x03
+#define  RTCSA_8192      0x03	/* 8192 Hz interrupt */
 #define  RTCSA_4096      0x04
 #define  RTCSA_2048      0x05
 #define  RTCSA_1024      0x06	/* default for profiling */
@@ -70,17 +71,17 @@
 #define  RTCSA_NOPROF	 RTCSA_128
 #define  RTC_NOPROFRATE  128
 #define  RTCSA_64        0x0a
-#define  RTCSA_32        0x0b
+#define  RTCSA_32        0x0b	/* 32Hz interrupt */
 
 #define RTC_STATUSB	0x0b	/* status register B */
-#define	 RTCSB_DST	 0x01	/* Daylight Savings Time enable	*/
+#define	 RTCSB_DST	 0x01	/* USA Daylight Savings Time enable */
 #define	 RTCSB_24HR	 0x02	/* 0 = 12 hours, 1 = 24	hours */
 #define	 RTCSB_BCD	 0x04	/* 0 = BCD, 1 =	Binary coded time */
 #define	 RTCSB_SQWE	 0x08	/* 1 = output sqare wave at SQW	pin */
 #define	 RTCSB_UINTR	 0x10	/* 1 = enable update-ended interrupt */
 #define	 RTCSB_AINTR	 0x20	/* 1 = enable alarm interrupt */
 #define	 RTCSB_PINTR	 0x40	/* 1 = enable periodic clock interrupt */
-#define  RTCSB_HALT      0x80	/* stop clock updates */
+#define  RTCSB_HALT      0x80	/* 1 = stop clock updates */
 
 #define RTC_INTR	0x0c	/* status register C (R) interrupt source */
 #define  RTCIR_UPDATE	 0x10	/* update intr */
@@ -89,8 +90,9 @@
 #define  RTCIR_INT	 0x80	/* interrupt output signal */
 
 #define RTC_STATUSD	0x0d	/* status register D (R) Lost Power */
-#define  RTCSD_PWR	 0x80	/* clock lost power */
+#define  RTCSD_PWR	 0x80	/* 0 = clock lost power */
 
+/* everything below here is CMOS RAM */
 #define RTC_DIAG	0x0e	/* status register E - bios diagnostic */
 #define RTCDG_BITS	"\020\010clock_battery\007ROM_cksum\006config_unit\005memory_size\004fixed_disk\003invalid_time"
 
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