Date: Thu, 13 Jan 2011 15:17:29 +0000 (UTC) From: "Jayachandran C." <jchandra@FreeBSD.org> To: cvs-src-old@freebsd.org Subject: cvs commit: src/sys/mips/include _types.h cpufunc.h param.h proc.h pte.h src/sys/mips/mips dump_machdep.c exception.S machdep.c pmap.c swtch.S src/sys/mips/rmi xlr_machdep.c Message-ID: <201101131517.p0DFHjrk099365@repoman.freebsd.org>
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jchandra 2011-01-13 15:17:29 UTC
FreeBSD src repository
Modified files:
sys/mips/include _types.h cpufunc.h param.h proc.h pte.h
sys/mips/mips dump_machdep.c exception.S machdep.c
pmap.c swtch.S
sys/mips/rmi xlr_machdep.c
Log:
SVN rev 217354 on 2011-01-13 15:17:29Z by jchandra
Support for 64 bit PTEs on n32 and n64 compilation.
In n32 and n64, add support for physical address above 4GB by having
64 bit page table entries and physical addresses. Major changes are:
- param.h: update PTE sizes, masks and shift values to support 64 bit PTEs.
- param.h: remove DELAY(), mips_btop(same as atop), mips_ptob (same as
ptoa), and reformat.
- param.h: remove casting to unsigned long in trunc_page and round_page
since this will be used on physical addresses.
- _types.h: have 64 bit __vm_paddr_t for n32.
- pte.h: update TLB LO0/1 access macros to support 64 bit PTE
- pte.h: assembly macros for PTE operations.
- proc.h: md_upte is now 64 bit for n32 and n64.
- exception.S and swtch.S: use the new PTE macros for PTE operations.
- cpufunc.h: TLB_LO0/1 registers are 64bit for n32 and n64.
- xlr_machdep.c: Add memory segments above 4GB to phys_avail[] as they are
supported now.
Reviewed by: jmallett (earlier version)
Revision Changes Path
1.5 +6 -2 src/sys/mips/include/_types.h
1.12 +8 -4 src/sys/mips/include/cpufunc.h
1.18 +37 -36 src/sys/mips/include/param.h
1.7 +13 -9 src/sys/mips/include/proc.h
1.13 +50 -13 src/sys/mips/include/pte.h
1.4 +1 -1 src/sys/mips/mips/dump_machdep.c
1.27 +31 -46 src/sys/mips/mips/exception.S
1.40 +3 -2 src/sys/mips/mips/machdep.c
1.89 +1 -1 src/sys/mips/mips/pmap.c
1.16 +7 -6 src/sys/mips/mips/swtch.S
1.28 +2 -0 src/sys/mips/rmi/xlr_machdep.c
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