Date: Mon, 24 Feb 2014 03:51:31 +0000 (UTC) From: Ian Lepore <ian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r262427 - head/sys/arm/freescale/imx Message-ID: <201402240351.s1O3pVIO096718@svn.freebsd.org>
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Author: ian Date: Mon Feb 24 03:51:31 2014 New Revision: 262427 URL: http://svnweb.freebsd.org/changeset/base/262427 Log: Add the bits needed to run SMP on imx6. The 'option SMP' isn't added to the kernel config yet; people wanting to test this have to opt-in for now. Added: head/sys/arm/freescale/imx/imx6_mp.c (contents, props changed) Modified: head/sys/arm/freescale/imx/files.imx6 head/sys/arm/freescale/imx/std.imx6 Modified: head/sys/arm/freescale/imx/files.imx6 ============================================================================== --- head/sys/arm/freescale/imx/files.imx6 Mon Feb 24 03:47:39 2014 (r262426) +++ head/sys/arm/freescale/imx/files.imx6 Mon Feb 24 03:51:31 2014 (r262427) @@ -22,6 +22,7 @@ arm/freescale/imx/common.c standard arm/freescale/imx/imx6_anatop.c standard arm/freescale/imx/imx6_ccm.c standard arm/freescale/imx/imx6_machdep.c standard +arm/freescale/imx/imx6_mp.c optional smp arm/freescale/imx/imx6_pl310.c standard arm/freescale/imx/imx_machdep.c standard arm/freescale/imx/imx_gpt.c standard Added: head/sys/arm/freescale/imx/imx6_mp.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/arm/freescale/imx/imx6_mp.c Mon Feb 24 03:51:31 2014 (r262427) @@ -0,0 +1,166 @@ +/*- + * Copyright (c) 2014 Juergen Weiss <weiss@uni-mainz.de> + * Copyright (c) 2014 Ian Lepore <ian@freebsd.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/lock.h> +#include <sys/mutex.h> +#include <sys/smp.h> + +#include <machine/smp.h> +#include <machine/fdt.h> +#include <machine/intr.h> + +#define SCU_PHYSBASE 0x00a00000 +#define SCU_SIZE 0x00001000 + +#define SCU_CONTROL_REG 0x00 +#define SCU_CONTROL_ENABLE (1 << 0) +#define SCU_CONFIG_REG 0x04 +#define SCU_CONFIG_REG_NCPU_MASK 0x03 +#define SCU_CPUPOWER_REG 0x08 +#define SCU_INV_TAGS_REG 0x0c +#define SCU_DIAG_CONTROL 0x30 +#define SCU_DIAG_DISABLE_MIGBIT (1 << 0) +#define SCU_FILTER_START_REG 0x40 +#define SCU_FILTER_END_REG 0x44 +#define SCU_SECURE_ACCESS_REG 0x50 +#define SCU_NONSECURE_ACCESS_REG 0x54 + +#define SRC_PHYSBASE 0x020d8000 +#define SRC_SIZE 0x4000 +#define SRC_CONTROL_REG 0x00 +#define SRC_CONTROL_C1ENA_SHIFT 22 /* Bit for Core 1 enable */ +#define SRC_CONTROL_C1RST_SHIFT 14 /* Bit for Core 1 reset */ +#define SRC_GPR0_C1FUNC 0x20 /* Register for Core 1 entry func */ +#define SRC_GPR1_C1ARG 0x24 /* Register for Core 1 entry arg */ + +void +platform_mp_init_secondary(void) +{ + + gic_init_secondary(); +} + +void +platform_mp_setmaxid(void) +{ + bus_space_handle_t scu; + uint32_t val; + + /* If we've already set the global vars don't bother to do it again. */ + if (mp_ncpus != 0) + return; + + if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0) + panic("Couldn't map the SCU\n"); + val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONFIG_REG); + bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE); + + mp_maxid = (val & SCU_CONFIG_REG_NCPU_MASK); + mp_ncpus = mp_maxid + 1; +} + +int +platform_mp_probe(void) +{ + + /* I think platform_mp_setmaxid must get called first, but be safe. */ + if (mp_ncpus == 0) + platform_mp_setmaxid(); + + return (mp_ncpus > 1); +} + +void +platform_mp_start_ap(void) +{ + bus_space_handle_t scu; + bus_space_handle_t src; + + uint32_t val; + int i; + + if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0) + panic("Couldn't map the SCU\n"); + if (bus_space_map(fdtbus_bs_tag, SRC_PHYSBASE, SRC_SIZE, 0, &src) != 0) + panic("Couldn't map the system reset controller (SRC)\n"); + + /* + * Invalidate SCU cache tags. The 0x0000fff0 constant invalidates all + * ways on all cores 1-3 (leaving core 0 alone). Per the ARM docs, it's + * harmless to write to the bits for cores that are not present. + */ + bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000fff0); + + /* + * Erratum ARM/MP: 764369 (problems with cache maintenance). + * Setting the "disable-migratory bit" in the undocumented SCU + * Diagnostic Control Register helps work around the problem. + */ + val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL); + bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, + val | SCU_DIAG_DISABLE_MIGBIT); + + /* Enable the SCU. */ + val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG); + bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG, + val | SCU_CONTROL_ENABLE); + + cpu_idcache_wbinv_all(); + cpu_l2cache_wbinv_all(); + + /* + * For each AP core, set the entry point address and argument registers, + * and set the core-enable and core-reset bits in the control register. + */ + val = bus_space_read_4(fdtbus_bs_tag, src, SRC_CONTROL_REG); + for (i=1; i < mp_ncpus; i++) { + bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR0_C1FUNC + 8*i, + pmap_kextract((vm_offset_t)mpentry)); + bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR1_C1ARG + 8*i, 0); + + val |= ((1 << (SRC_CONTROL_C1ENA_SHIFT - 1 + i )) | + ( 1 << (SRC_CONTROL_C1RST_SHIFT - 1 + i))); + + } + bus_space_write_4(fdtbus_bs_tag, src, 0, val); + + armv7_sev(); + + bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE); + bus_space_unmap(fdtbus_bs_tag, src, SRC_SIZE); +} + +void +platform_ipi_send(cpuset_t cpus, u_int ipi) +{ + + pic_ipi_send(cpus, ipi); +} Modified: head/sys/arm/freescale/imx/std.imx6 ============================================================================== --- head/sys/arm/freescale/imx/std.imx6 Mon Feb 24 03:47:39 2014 (r262426) +++ head/sys/arm/freescale/imx/std.imx6 Mon Feb 24 03:51:31 2014 (r262427) @@ -10,5 +10,8 @@ options KERNPHYSADDR = 0x12000000 makeoptions KERNPHYSADDR = 0x12000000 options PHYSADDR = 0x10000000 +options IPI_IRQ_START=0 +options IPI_IRQ_END=15 + files "../freescale/imx/files.imx6"
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