Date: Mon, 14 Jul 2014 07:27:11 +0000 (UTC) From: Hans Petter Selasky <hselasky@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-8@freebsd.org Subject: svn commit: r268603 - stable/8/sys/dev/usb/controller Message-ID: <201407140727.s6E7RBdL095763@svn.freebsd.org>
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Author: hselasky Date: Mon Jul 14 07:27:10 2014 New Revision: 268603 URL: http://svnweb.freebsd.org/changeset/base/268603 Log: MFC r268354: Improve support for Intel Lynx Point USB 3.0 controllers by masking the port routing bits like done in Linux. Modified: stable/8/sys/dev/usb/controller/xhci_pci.c stable/8/sys/dev/usb/controller/xhcireg.h Directory Properties: stable/8/sys/ (props changed) stable/8/sys/dev/ (props changed) stable/8/sys/dev/usb/ (props changed) Modified: stable/8/sys/dev/usb/controller/xhci_pci.c ============================================================================== --- stable/8/sys/dev/usb/controller/xhci_pci.c Mon Jul 14 07:25:30 2014 (r268602) +++ stable/8/sys/dev/usb/controller/xhci_pci.c Mon Jul 14 07:27:10 2014 (r268603) @@ -147,6 +147,9 @@ xhci_pci_port_route(device_t self, uint3 temp |= set; temp &= ~clear; + /* Don't set bits which the hardware doesn't support */ + temp &= pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4); + pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp, 4); pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp, 4); Modified: stable/8/sys/dev/usb/controller/xhcireg.h ============================================================================== --- stable/8/sys/dev/usb/controller/xhcireg.h Mon Jul 14 07:25:30 2014 (r268602) +++ stable/8/sys/dev/usb/controller/xhcireg.h Mon Jul 14 07:27:10 2014 (r268603) @@ -35,7 +35,9 @@ #define PCI_XHCI_FLADJ 0x61 /* RW frame length adjust */ #define PCI_XHCI_INTEL_XUSB2PR 0xD0 /* Intel USB2 Port Routing */ +#define PCI_XHCI_INTEL_USB2PRM 0xD4 /* Intel USB2 Port Routing Mask */ #define PCI_XHCI_INTEL_USB3_PSSEN 0xD8 /* Intel USB3 Port SuperSpeed Enable */ +#define PCI_XHCI_INTEL_USB3PRM 0xDC /* Intel USB3 Port Routing Mask */ /* XHCI capability registers */ #define XHCI_CAPLENGTH 0x00 /* RO capability */
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