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Date:      Mon, 14 Jul 2014 07:30:05 +0000 (UTC)
From:      Hans Petter Selasky <hselasky@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org
Subject:   svn commit: r268604 - stable/10/sys/dev/usb/controller
Message-ID:  <201407140730.s6E7U5f9096283@svn.freebsd.org>

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Author: hselasky
Date: Mon Jul 14 07:30:04 2014
New Revision: 268604
URL: http://svnweb.freebsd.org/changeset/base/268604

Log:
  MFC r268354:
  Improve support for Intel Lynx Point USB 3.0 controllers by masking
  the port routing bits like done in Linux.

Modified:
  stable/10/sys/dev/usb/controller/xhci_pci.c
  stable/10/sys/dev/usb/controller/xhcireg.h
Directory Properties:
  stable/10/   (props changed)

Modified: stable/10/sys/dev/usb/controller/xhci_pci.c
==============================================================================
--- stable/10/sys/dev/usb/controller/xhci_pci.c	Mon Jul 14 07:27:10 2014	(r268603)
+++ stable/10/sys/dev/usb/controller/xhci_pci.c	Mon Jul 14 07:30:04 2014	(r268604)
@@ -157,6 +157,9 @@ xhci_pci_port_route(device_t self, uint3
 	temp |= set;
 	temp &= ~clear;
 
+	/* Don't set bits which the hardware doesn't support */
+	temp &= pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4);
+
 	pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp, 4);
 	pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp, 4);
 

Modified: stable/10/sys/dev/usb/controller/xhcireg.h
==============================================================================
--- stable/10/sys/dev/usb/controller/xhcireg.h	Mon Jul 14 07:27:10 2014	(r268603)
+++ stable/10/sys/dev/usb/controller/xhcireg.h	Mon Jul 14 07:30:04 2014	(r268604)
@@ -35,7 +35,9 @@
 #define	PCI_XHCI_FLADJ		0x61	/* RW frame length adjust */
 
 #define	PCI_XHCI_INTEL_XUSB2PR	0xD0	/* Intel USB2 Port Routing */
+#define	PCI_XHCI_INTEL_USB2PRM	0xD4	/* Intel USB2 Port Routing Mask */
 #define	PCI_XHCI_INTEL_USB3_PSSEN 0xD8	/* Intel USB3 Port SuperSpeed Enable */
+#define	PCI_XHCI_INTEL_USB3PRM	0xDC	/* Intel USB3 Port Routing Mask */
 
 /* XHCI capability registers */
 #define	XHCI_CAPLENGTH		0x00	/* RO capability */



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