Date: Tue, 15 Jun 2004 09:36:21 GMT From: Juli Mallett <jmallett@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 55000 for review Message-ID: <200406150936.i5F9aLAI007134@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=55000 Change 55000 by jmallett@jmallett_oingo on 2004/06/15 09:35:25 Take a major axe across one of the bigger chunks of NetBSD code. Severely cripple ability to deal with "modern" MIPS32/MIPS64 chips and concentrate on the R4400 and similar that are much more comfortable for trying to get *one thing right* right now. I can abstract work as much as I need to support more in the future, of course, this is all just here as a result of using some NetBSD code as a crutch. I need to get on from that so I can get to understanding all the stuff I've done and simplifying all the interactions. Hell, we still don't even run cached! Affected files ... .. //depot/projects/mips/sys/conf/files.mips#36 edit .. //depot/projects/mips/sys/mips/include/cpu.h#17 edit .. //depot/projects/mips/sys/mips/include/md_var.h#10 edit .. //depot/projects/mips/sys/mips/mips/cache.c#7 edit .. //depot/projects/mips/sys/mips/mips/cpu.c#1 add .. //depot/projects/mips/sys/mips/mips/db_interface.c#15 edit .. //depot/projects/mips/sys/mips/mips/machdep.c#44 edit Differences ... ==== //depot/projects/mips/sys/conf/files.mips#36 (text+ko) ==== @@ -13,6 +13,7 @@ mips/mips/autoconf.c standard mips/mips/bus_machdep.c standard mips/mips/busdma_machdep.c standard +mips/mips/cpu.c standard mips/mips/critical.c standard mips/mips/elf_machdep.c standard mips/mips/exception.S standard ==== //depot/projects/mips/sys/mips/include/cpu.h#17 (text+ko) ==== @@ -86,48 +86,6 @@ return (++now); } -/* - * Macros to find the CPU architecture we're on at run-time, - * or if possible, at compile-time. - */ - -#define CPU_ARCH_MIPSx 0 /* XXX unknown */ -#define CPU_ARCH_MIPS1 (1 << 0) -#define CPU_ARCH_MIPS2 (1 << 1) -#define CPU_ARCH_MIPS3 (1 << 2) -#define CPU_ARCH_MIPS4 (1 << 3) -#define CPU_ARCH_MIPS5 (1 << 4) -#define CPU_ARCH_MIPS32 (1 << 5) -#define CPU_ARCH_MIPS64 (1 << 6) - -#ifndef LOCORE -/* XXX simonb - * Should the following be in a cpu_info type structure? - * And how many of these are per-cpu vs. per-system? (Ie, - * we can assume that all cpus have the same mmu-type, but - * maybe not that all cpus run at the same clock speed. - * Some SGI's apparently support R12k and R14k in the same - * box.) - */ -extern int cpu_arch; -extern int mips_cpu_flags; -extern int mips_has_r4k_mmu; -#define MIPS_HAS_R4K_MMU (mips_has_r4k_mmu) -extern int mips_has_llsc; -#define MIPS_HAS_LLSC (mips_has_llsc) -extern int mips3_pg_cached; - -#define CPU_MIPS_R4K_MMU 0x0001 -#define CPU_MIPS_NO_LLSC 0x0002 -#define CPU_MIPS_CAUSE_IV 0x0004 -#define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ -#define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ -#define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ -#define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ -#define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ -#define MIPS_NOT_SUPP 0x8000 -#endif - void fork_trampoline(void); void cpu_halt(void); void cpu_reset(void); ==== //depot/projects/mips/sys/mips/include/md_var.h#10 (text+ko) ==== @@ -36,6 +36,8 @@ extern int cpu_id; extern int fpu_id; +void cpu_identify(void); +void mips_cpu_init(void); void mips_init(void); /* Platform call-downs. */ ==== //depot/projects/mips/sys/mips/mips/cache.c#7 (text+ko) ==== @@ -141,7 +141,6 @@ void mips3_get_cache_config(int); static void mips_config_cache_prehistoric(void); -static void mips_config_cache_modern(void); /* * mips_dcache_compute_align: @@ -179,7 +178,7 @@ if (MIPS_PRID_CID(cpu_id) == MIPS_PRID_CID_PREHISTORIC) mips_config_cache_prehistoric(); if (MIPS_PRID_CID(cpu_id) != MIPS_PRID_CID_PREHISTORIC) - mips_config_cache_modern(); + panic("don't support modern MIPS CPUs yet"); #ifdef DIAGNOSTIC /* Check that all cache ops are set up. */ @@ -612,205 +611,3 @@ static void cache_noop(void) __attribute__((__unused__)); static void cache_noop(void) {} - -static void -mips_config_cache_modern(void) -{ - /* MIPS32/MIPS64, use coprocessor 0 config registers */ - uint32_t cfg, cfg1; - - cfg = mips_rd_config(); - cfg1 = mipsNN_cp0_config1_read(); - -#ifdef MIPS_DISABLE_L1_CACHE - cfg1 &= ~MIPSNN_CFG1_IL_MASK; - cfg1 &= ~MIPSNN_CFG1_DL_MASK; - mipsNN_cp0_config1_write(cfg1); -#endif - - /* figure out Dcache params. */ - switch (MIPSNN_GET(CFG1_DL, cfg1)) { - case MIPSNN_CFG1_DL_NONE: - mips_pdcache_line_size = mips_pdcache_way_size = - mips_pdcache_ways = 0; - break; - case MIPSNN_CFG1_DL_RSVD: - panic("reserved MIPS32/64 Dcache line size"); - break; - default: - if (MIPSNN_GET(CFG1_DS, cfg1) == MIPSNN_CFG1_DS_RSVD) - panic("reserved MIPS32/64 Dcache sets per way"); - mips_pdcache_line_size = MIPSNN_CFG1_DL(cfg1); - mips_pdcache_way_size = - mips_pdcache_line_size * MIPSNN_CFG1_DS(cfg1); - mips_pdcache_ways = MIPSNN_CFG1_DA(cfg1) + 1; - - /* - * Compute the total size and "way mask" for the - * primary Icache. - */ - mips_pdcache_size = - mips_pdcache_way_size * mips_pdcache_ways; - mips_pdcache_way_mask = mips_pdcache_way_size - 1; - break; - } - - /* figure out Icache params. */ - switch (MIPSNN_GET(CFG1_IL, cfg1)) { - case MIPSNN_CFG1_IL_NONE: - mips_picache_line_size = mips_picache_way_size = - mips_picache_ways = 0; - break; - case MIPSNN_CFG1_IL_RSVD: - panic("reserved MIPS32/64 Icache line size"); - break; - default: - if (MIPSNN_GET(CFG1_IS, cfg1) == MIPSNN_CFG1_IS_RSVD) - panic("reserved MIPS32/64 Icache sets per way"); - mips_picache_line_size = MIPSNN_CFG1_IL(cfg1); - mips_picache_way_size = - mips_picache_line_size * MIPSNN_CFG1_IS(cfg1); - mips_picache_ways = MIPSNN_CFG1_IA(cfg1) + 1; - - /* - * Compute the total size and "way mask" for the - * primary Dcache. - */ - mips_picache_size = - mips_picache_way_size * mips_picache_ways; - mips_picache_way_mask = mips_picache_way_size - 1; - break; - } - -#define CACHE_DEBUG -#ifdef CACHE_DEBUG - printf("MIPS32/64 params: cpu arch: %d\n", cpu_arch); - printf("MIPS32/64 params: TLB entries: %d\n", mips_num_tlb_entries); - if (mips_picache_line_size == 0) - printf("MIPS32/64 params: no Icache\n"); - else { - printf("MIPS32/64 params: Icache: line = %d, total = %d, " - "ways = %d\n", mips_picache_line_size, - mips_picache_way_size * mips_picache_ways, - mips_picache_ways); - printf("\t\t sets = %d\n", (mips_picache_way_size * - mips_picache_ways / mips_picache_line_size) / - mips_picache_ways); - } - if (mips_pdcache_line_size == 0) - printf("MIPS32/64 params: no Dcache\n"); - else { - printf("MIPS32/64 params: Dcache: line = %d, total = %d, " - "ways = %d\n", mips_pdcache_line_size, - mips_pdcache_way_size * mips_pdcache_ways, - mips_pdcache_ways); - printf("\t\t sets = %d\n", (mips_pdcache_way_size * - mips_pdcache_ways / mips_pdcache_line_size) / - mips_pdcache_ways); - } -#endif /* CACHE_DEBUG */ - - switch (mips_picache_line_size) { - case 16: - mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_16; - mips_cache_ops.mco_icache_sync_range = - mipsNN_icache_sync_range_16; - mips_cache_ops.mco_icache_sync_range_index = - mipsNN_icache_sync_range_index_16; - break; - case 32: - mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_32; - mips_cache_ops.mco_icache_sync_range = - mipsNN_icache_sync_range_32; - mips_cache_ops.mco_icache_sync_range_index = - mipsNN_icache_sync_range_index_32; - break; -#ifdef MIPS_DISABLE_L1_CACHE - case 0: - mips_cache_ops.mco_icache_sync_all = (void *)(uintptr_t)cache_noop; - mips_cache_ops.mco_icache_sync_range = (void *)(uintptr_t)cache_noop; - mips_cache_ops.mco_icache_sync_range_index = (void *)(uintptr_t)cache_noop; - break; -#endif - default: - panic("no Icache ops for %d byte lines", - mips_picache_line_size); - } - - switch (mips_pdcache_line_size) { - case 16: - mips_cache_ops.mco_pdcache_wbinv_all = - mips_cache_ops.mco_intern_pdcache_wbinv_all = - mipsNN_pdcache_wbinv_all_16; - mips_cache_ops.mco_pdcache_wbinv_range = - mipsNN_pdcache_wbinv_range_16; - mips_cache_ops.mco_pdcache_wbinv_range_index = - mips_cache_ops.mco_intern_pdcache_wbinv_range_index = - mipsNN_pdcache_wbinv_range_index_16; - mips_cache_ops.mco_pdcache_inv_range = - mipsNN_pdcache_inv_range_16; - mips_cache_ops.mco_pdcache_wb_range = - mips_cache_ops.mco_intern_pdcache_wb_range = - mipsNN_pdcache_wb_range_16; - break; - case 32: - mips_cache_ops.mco_pdcache_wbinv_all = - mips_cache_ops.mco_intern_pdcache_wbinv_all = - mipsNN_pdcache_wbinv_all_32; - mips_cache_ops.mco_pdcache_wbinv_range = - mipsNN_pdcache_wbinv_range_32; - mips_cache_ops.mco_pdcache_wbinv_range_index = - mips_cache_ops.mco_intern_pdcache_wbinv_range_index = - mipsNN_pdcache_wbinv_range_index_32; - mips_cache_ops.mco_pdcache_inv_range = - mipsNN_pdcache_inv_range_32; - mips_cache_ops.mco_pdcache_wb_range = - mips_cache_ops.mco_intern_pdcache_wb_range = - mipsNN_pdcache_wb_range_32; - break; -#ifdef MIPS_DISABLE_L1_CACHE - case 0: - mips_cache_ops.mco_pdcache_wbinv_all = (void *)(uintptr_t)cache_noop; - mips_cache_ops.mco_intern_pdcache_wbinv_all = - (void *)(uintptr_t)cache_noop; - mips_cache_ops.mco_pdcache_wbinv_range = (void *)(uintptr_t)cache_noop; - mips_cache_ops.mco_pdcache_wbinv_range_index = - (void *)(uintptr_t)cache_noop; - mips_cache_ops.mco_intern_pdcache_wbinv_range_index = - (void *)(uintptr_t)cache_noop; - mips_cache_ops.mco_pdcache_inv_range = (void *)(uintptr_t)cache_noop; - mips_cache_ops.mco_pdcache_wb_range = (void *)(uintptr_t)cache_noop; - mips_cache_ops.mco_intern_pdcache_wb_range = (void *)(uintptr_t)cache_noop; - break; -#endif - default: - panic("no Dcache ops for %d byte lines", - mips_pdcache_line_size); - } - - mipsNN_cache_init(cfg, cfg1); - - if (mips_cpu_flags & - (CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_I_D_CACHE_COHERENT)) { -#ifdef CACHE_DEBUG - printf(" Dcache is coherent\n"); -#endif - mips_cache_ops.mco_pdcache_wbinv_all = (void *)(uintptr_t)cache_noop; - mips_cache_ops.mco_pdcache_wbinv_range = (void *)(uintptr_t)cache_noop; - mips_cache_ops.mco_pdcache_wbinv_range_index = - (void *)(uintptr_t)cache_noop; - mips_cache_ops.mco_pdcache_inv_range = (void *)(uintptr_t)cache_noop; - mips_cache_ops.mco_pdcache_wb_range = (void *)(uintptr_t)cache_noop; - } - if (mips_cpu_flags & CPU_MIPS_I_D_CACHE_COHERENT) { -#ifdef CACHE_DEBUG - printf(" Icache is coherent against Dcache\n"); -#endif - mips_cache_ops.mco_intern_pdcache_wbinv_all = - (void *)(uintptr_t)cache_noop; - mips_cache_ops.mco_intern_pdcache_wbinv_range_index = - (void *)(uintptr_t)cache_noop; - mips_cache_ops.mco_intern_pdcache_wb_range = - (void *)(uintptr_t)cache_noop; - } -} ==== //depot/projects/mips/sys/mips/mips/db_interface.c#15 (text+ko) ==== @@ -357,31 +357,21 @@ SHOW32(MIPS_COP_0_TLB_INDEX, "index"); SHOW32(MIPS_COP_0_TLB_RANDOM, "random"); - if (!MIPS_HAS_R4K_MMU) { - SHOW32(MIPS_COP_0_TLB_LOW, "entrylow"); - } else { - SHOW64(MIPS_COP_0_TLB_LO0, "entrylo0"); - SHOW64(MIPS_COP_0_TLB_LO1, "entrylo1"); - } + SHOW64(MIPS_COP_0_TLB_LO0, "entrylo0"); + SHOW64(MIPS_COP_0_TLB_LO1, "entrylo1"); SHOW64(MIPS_COP_0_TLB_CONTEXT, "context"); - if (MIPS_HAS_R4K_MMU) { - SHOW32(MIPS_COP_0_TLB_PG_MASK, "pagemask"); - SHOW32(MIPS_COP_0_TLB_WIRED, "wired"); - } + SHOW32(MIPS_COP_0_TLB_PG_MASK, "pagemask"); + SHOW32(MIPS_COP_0_TLB_WIRED, "wired"); SHOW64(MIPS_COP_0_BAD_VADDR, "badvaddr"); - if (cpu_arch >= CPU_ARCH_MIPS3) { - SHOW32(MIPS_COP_0_COUNT, "count"); - } + SHOW32(MIPS_COP_0_COUNT, "count"); SHOW64(MIPS_COP_0_TLB_HI, "entryhi"); - if (cpu_arch >= CPU_ARCH_MIPS3) { - SHOW32(MIPS_COP_0_COMPARE, "compare"); - } + SHOW32(MIPS_COP_0_COMPARE, "compare"); SHOW32(MIPS_COP_0_STATUS, "status"); SHOW32(MIPS_COP_0_CAUSE, "cause"); @@ -394,22 +384,20 @@ val = mipsNN_cp0_config1_read(); printf(" config1: %#x\n", val); - if (mips_has_llsc) { - SHOW64(MIPS_COP_0_LLADDR, "lladdr"); - SHOW64(MIPS_COP_0_WATCH_LO, "watchlo"); + SHOW64(MIPS_COP_0_LLADDR, "lladdr"); + SHOW64(MIPS_COP_0_WATCH_LO, "watchlo"); - SHOW32(MIPS_COP_0_WATCH_HI, "watchhi"); + SHOW32(MIPS_COP_0_WATCH_HI, "watchhi"); - SHOW64(MIPS_COP_0_TLB_XCONTEXT, "xcontext"); - SHOW64(MIPS_COP_0_PERFCNT, "perfcnt"); + SHOW64(MIPS_COP_0_TLB_XCONTEXT, "xcontext"); + SHOW64(MIPS_COP_0_PERFCNT, "perfcnt"); - SHOW32(MIPS_COP_0_ECC, "ecc"); - SHOW32(MIPS_COP_0_CACHE_ERR, "cacherr"); - SHOW32(MIPS_COP_0_TAG_LO, "cachelo"); - SHOW32(MIPS_COP_0_TAG_HI, "cachehi"); + SHOW32(MIPS_COP_0_ECC, "ecc"); + SHOW32(MIPS_COP_0_CACHE_ERR, "cacherr"); + SHOW32(MIPS_COP_0_TAG_LO, "cachelo"); + SHOW32(MIPS_COP_0_TAG_HI, "cachehi"); - SHOW64(MIPS_COP_0_ERROR_PC, "errorpc"); - } + SHOW64(MIPS_COP_0_ERROR_PC, "errorpc"); } /* ==== //depot/projects/mips/sys/mips/mips/machdep.c#44 (text+ko) ==== @@ -1,121 +1,4 @@ -/* - * Copyright 2002 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Simon Burge for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Copyright 2000, 2001 - * Broadcom Corporation. All rights reserved. - * - * This software is furnished under license and may be used and copied only - * in accordance with the following terms and conditions. Subject to these - * conditions, you may download, copy, install, use, modify and distribute - * modified or unmodified copies of this software in source and/or binary - * form. No title or ownership is transferred hereby. - * - * 1) Any source code used, modified or distributed must reproduce and - * retain this copyright notice and list of conditions as they appear in - * the source file. - * - * 2) No right is granted to use any trade name, trademark, or logo of - * Broadcom Corporation. The "Broadcom Corporation" name may not be - * used to endorse or promote products derived from this software - * without the prior written permission of Broadcom Corporation. - * - * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR - * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE - * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE - * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - /*- - * Copyright (c) 1998, 2001 The NetBSD Foundation, Inc. - * All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, - * NASA Ames Research Center and by Chris Demetriou. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the NetBSD - * Foundation, Inc. and its contributors. - * 4. Neither the name of The NetBSD Foundation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Copyright 1996 The Board of Trustees of The Leland Stanford - * Junior University. All Rights Reserved. - * - * Permission to use, copy, modify, and distribute this - * software and its documentation for any purpose and without - * fee is hereby granted, provided that the above copyright - * notice appear in all copies. Stanford University - * makes no representations about the suitability of this - * software for any purpose. It is provided "as is" without - * express or implied warranty. - */ - -/*- * Copyright (c) 2002 Juli Mallett <jmallett@FreeBSD.org> * All rights reserved. * @@ -179,15 +62,7 @@ #include <ddb/ddb.h> #endif -int cpu_arch; -int mips_cpu_flags; -int mips_has_r4k_mmu; -int mips_has_llsc; - -int mips_num_tlb_entries; - int cold = 1; -int cpu_id, fpu_id; static struct pcpu pcpu0; struct pcpu *pcpup = &pcpu0; @@ -201,8 +76,6 @@ vm_size_t physsz; -static void mips_vector_init(void); -static void cpu_identify(void); void cpu_startup(void *); SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); @@ -211,7 +84,7 @@ { physmem = btoc(physsz); - mips_vector_init(); + mips_cpu_init(); pmap_bootstrap(); proc_linkup(&proc0, &ksegrp0, &kse0, &thread0); @@ -232,6 +105,7 @@ cpu_startup(void *dummy) { cpu_identify(); + platform_identify(); printf("real memory = %lu (%lu MB)\n", physsz, physsz / (1024 * 1024)); @@ -349,501 +223,3 @@ { return (-1); } - -/* - * XXX begin NetBSD stuff, I want to rewrite or move out most. - */ - -struct pridtab { - int cpu_cid; - int cpu_pid; - int cpu_rev; /* -1 == wildcard */ - int cpu_copts; /* -1 == wildcard */ - int cpu_isa; /* -1 == probed (mips32/mips64) */ - int cpu_ntlb; /* -1 == unknown, 0 == probed */ - int cpu_flags; - char *cpu_name; -}; - -/* - * Assumptions: - * - All MIPS3+ have an r4k-style MMU. _Many_ assumptions throughout - * much of the mips code about this. Includes overloaded usage of - * MIPS_PLUS. - * - All MIPS3+ use the same exception model (cp0 status, cause bits, - * etc). _Many_ assumptions throughout much of the mips code about - * this. Includes overloaded usage of MIPS_PLUS. - * - All MIPS3+ have a count register. MIPS_HAS_CLOCK in <mips/cpu.h> - * will need to be revised if this is false. - */ -#define MIPS32_FLAGS CPU_MIPS_R4K_MMU | CPU_MIPS_CAUSE_IV | CPU_MIPS_USE_WAIT -#define MIPS64_FLAGS MIPS32_FLAGS /* same as MIPS32 flags (for now) */ - -static const struct pridtab *mycpu; - -static const struct pridtab cputab[] = { - { 0, MIPS_R2000, -1, -1, CPU_ARCH_MIPS1, 64, - CPU_MIPS_NO_LLSC, "MIPS R2000 CPU" }, - { 0, MIPS_R3000, MIPS_REV_R3000, -1, CPU_ARCH_MIPS1, 64, - CPU_MIPS_NO_LLSC, "MIPS R3000 CPU" }, - { 0, MIPS_R3000, MIPS_REV_R3000A, -1, CPU_ARCH_MIPS1, 64, - CPU_MIPS_NO_LLSC, "MIPS R3000A CPU" }, - { 0, MIPS_R6000, -1, -1, CPU_ARCH_MIPS2, 32, - MIPS_NOT_SUPP, "MIPS R6000 CPU" }, - - /* - * rev 0x00 and 0x30 are R4000, 0x40, 0x50 and 0x60 are R4400. - * should we allow ranges and use 0x00 - 0x3f for R4000 and - * 0x40 - 0xff for R4400? - */ - { 0, MIPS_R4000, MIPS_REV_R4000_A, -1, CPU_ARCH_MIPS3, 48, - CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, - "MIPS R4000 CPU" }, - { 0, MIPS_R4000, MIPS_REV_R4000_B, -1, CPU_ARCH_MIPS3, 48, - CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, - "MIPS R4000 CPU" }, - { 0, MIPS_R4000, MIPS_REV_R4400_A, -1, CPU_ARCH_MIPS3, 48, - CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, - "MIPS R4400 CPU" }, - { 0, MIPS_R4000, MIPS_REV_R4400_B, -1, CPU_ARCH_MIPS3, 48, - CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, - "MIPS R4400 CPU" }, - { 0, MIPS_R4000, MIPS_REV_R4400_C, -1, CPU_ARCH_MIPS3, 48, - CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, - "MIPS R4400 CPU" }, - - { 0, MIPS_R3LSI, -1, -1, CPU_ARCH_MIPS1, -1, - MIPS_NOT_SUPP, "LSI Logic R3000 derivative" }, - { 0, MIPS_R6000A, -1, -1, CPU_ARCH_MIPS2, 32, - MIPS_NOT_SUPP, "MIPS R6000A CPU" }, - { 0, MIPS_R3IDT, -1, -1, CPU_ARCH_MIPS1, -1, - MIPS_NOT_SUPP, "IDT R3041 or RC36100 CPU" }, - { 0, MIPS_R4100, -1, -1, CPU_ARCH_MIPS3, 32, - CPU_MIPS_R4K_MMU | CPU_MIPS_NO_LLSC, "NEC VR4100 CPU" }, - { 0, MIPS_R4200, -1, -1, CPU_ARCH_MIPS3, -1, - MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "NEC VR4200 CPU" }, - { 0, MIPS_R4300, -1, -1, CPU_ARCH_MIPS3, 32, - CPU_MIPS_R4K_MMU, "NEC VR4300 CPU" }, - { 0, MIPS_R4600, -1, -1, CPU_ARCH_MIPS3, 48, - CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, - "QED R4600 Orion CPU" }, - { 0, MIPS_R4700, -1, -1, CPU_ARCH_MIPS3, 48, - CPU_MIPS_R4K_MMU, "QED R4700 Orion CPU" }, - - { 0, MIPS_R8000, -1, -1, CPU_ARCH_MIPS4, 384, - MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "MIPS R8000 Blackbird/TFP CPU" }, - { 0, MIPS_R10000, -1, -1, CPU_ARCH_MIPS4, 64, - MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "MIPS R10000 CPU" }, - { 0, MIPS_R12000, -1, -1, CPU_ARCH_MIPS4, 64, - MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "MIPS R12000 CPU" }, - { 0, MIPS_R14000, -1, -1, CPU_ARCH_MIPS4, 64, - MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "MIPS R14000 CPU" }, - - /* XXX - * If the Processor Revision ID of the 4650 isn't 0, the following - * entry needs to be adjusted. Can't use a wildcard match because - * the TX39 series processors share the same Processor ID value. - * Or maybe put TX39 CPUs first if the revid doesn't overlap with - * the 4650... - */ - { 0, MIPS_R4650, 0, -1, CPU_ARCH_MIPS3, -1, - MIPS_NOT_SUPP /* no MMU! */, "QED R4650 CPU" }, - { 0, MIPS_TX3900, MIPS_REV_TX3912, -1, CPU_ARCH_MIPS1, 32, - CPU_MIPS_NO_LLSC, "Toshiba TX3912 CPU" }, - { 0, MIPS_TX3900, MIPS_REV_TX3922, -1, CPU_ARCH_MIPS1, 64, - CPU_MIPS_NO_LLSC, "Toshiba TX3922 CPU" }, - { 0, MIPS_TX3900, MIPS_REV_TX3927, -1, CPU_ARCH_MIPS1, 64, - CPU_MIPS_NO_LLSC, "Toshiba TX3927 CPU" }, - { 0, MIPS_R5000, -1, -1, CPU_ARCH_MIPS4, 48, - CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, - "MIPS R5000 CPU" }, - { 0, MIPS_RM5200, -1, -1, CPU_ARCH_MIPS4, 48, - CPU_MIPS_R4K_MMU | CPU_MIPS_CAUSE_IV | CPU_MIPS_DOUBLE_COUNT | - CPU_MIPS_USE_WAIT, "QED RM5200 CPU" }, - - /* XXX - * The rm7000 rev 2.0 can have 64 tlbs, and has 6 extra interrupts. See - * "Migrating to the RM7000 from other MIPS Microprocessors" - * for more details. - */ - { 0, MIPS_RM7000, -1, -1, CPU_ARCH_MIPS4, 48, - MIPS_NOT_SUPP | CPU_MIPS_CAUSE_IV | CPU_MIPS_DOUBLE_COUNT | - CPU_MIPS_USE_WAIT, "QED RM7000 CPU" }, - - /* - * IDT RC32300 core is a 32 bit MIPS2 processor with - * MIPS3/MIPS4 extensions. It has an R4000-style TLB, - * while all registers are 32 bits and any 64 bit - * instructions like ld/sd/dmfc0/dmtc0 are not allowed. - * - * note that the Config register has a non-standard base - * for IC and DC (2^9 instead of 2^12). - * - */ - { 0, MIPS_RC32300, -1, -1, CPU_ARCH_MIPS3, 16, - MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "IDT RC32300 CPU" }, - { 0, MIPS_RC32364, -1, -1, CPU_ARCH_MIPS3, 16, - MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "IDT RC32364 CPU" }, - { 0, MIPS_RC64470, -1, -1, CPU_ARCH_MIPSx, -1, - MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "IDT RC64474/RC64475 CPU" }, - - { 0, MIPS_R5400, -1, -1, CPU_ARCH_MIPSx, -1, - MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, "NEC VR5400 CPU" }, - { 0, MIPS_R5900, -1, -1, CPU_ARCH_MIPS3, 48, - CPU_MIPS_NO_LLSC | CPU_MIPS_R4K_MMU, "Toshiba R5900 CPU" }, - - { 0, MIPS_TX4900, MIPS_REV_TX4927, -1, CPU_ARCH_MIPS3, 48, - CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, - "Toshiba TX4927 CPU" }, - { 0, MIPS_TX4900, -1, -1, CPU_ARCH_MIPS3, 48, - CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, - "Toshiba TX4900 CPU" }, - -#if 0 /* ID collisions : can we use a CU1 test or similar? */ - { 0, MIPS_R3SONY, -1, -1, CPU_ARCH_MIPS1, -1, - MIPS_NOT_SUPP, "SONY R3000 derivative" }, /* 0x21; crash R4700? */ - { 0, MIPS_R3NKK, -1, -1, CPU_ARCH_MIPS1, -1, - MIPS_NOT_SUPP, "NKK R3000 derivative" }, /* 0x23; crash R5000? */ -#endif - - { MIPS_PRID_CID_MTI, MIPS_4Kc, -1, -1, -1, 0, - MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, "4Kc" }, - { MIPS_PRID_CID_MTI, MIPS_4KEc, -1, -1, -1, 0, - MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, "4KEc" }, - { MIPS_PRID_CID_MTI, MIPS_4KSc, -1, -1, -1, 0, - MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, "4KSc" }, - { MIPS_PRID_CID_MTI, MIPS_5Kc, -1, -1, -1, 0, - MIPS64_FLAGS | CPU_MIPS_DOUBLE_COUNT, "5Kc" }, - { MIPS_PRID_CID_MTI, MIPS_20Kc, -1, -1, -1, 0, - MIPS64_FLAGS, "20Kc" }, - - { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1000, -1, 0, - MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, - "Au1000 (Rev 1 core)" }, - { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1000, -1, 0, - MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, - "Au1000 (Rev 2 core)" }, - - { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1500, -1, 0, - MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, - "Au1500 (Rev 1 core)" }, - { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1500, -1, 0, - MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, - "Au1500 (Rev 2 core)" }, - - { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1100, -1, 0, - MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, - "Au1100 (Rev 1 core)" }, - { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1100, -1, 0, - MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, - "Au1100 (Rev 2 core)" }, - - { 0, 0, 0, 0, 0, 0, - 0, NULL } -}; - -static const struct pridtab fputab[] = { - { 0, MIPS_SOFT, -1, 0, 0, 0, 0, "software emulated floating point" }, - { 0, MIPS_R2360, -1, 0, 0, 0, 0, "MIPS R2360 Floating Point Board" }, - { 0, MIPS_R2010, -1, 0, 0, 0, 0, "MIPS R2010 FPC" }, - { 0, MIPS_R3010, -1, 0, 0, 0, 0, "MIPS R3010 FPC" }, - { 0, MIPS_R6010, -1, 0, 0, 0, 0, "MIPS R6010 FPC" }, - { 0, MIPS_R4010, -1, 0, 0, 0, 0, "MIPS R4010 FPC" }, -}; - -/* - * Company ID's are not sparse (yet), this array is indexed directly - * by pridtab->cpu_cid. - */ -static const char *cidnames[] = { - "Prehistoric", - "MIPS", /* or "MIPS Technologies, Inc. */ - "Broadcom", /* or "Broadcom Corp." */ - "Alchemy", /* or "Alchemy Semiconductor" */ - "SiByte", /* or "Broadcom Corp. (SiByte)" */ - "SandCraft", -}; -#define ncidnames (sizeof(cidnames) / sizeof(cidnames[0])) - -static void -mips_vector_install(vm_offset_t addr, char *begin, char *end) -{ - size_t len, max; - - max = 0x80; - len = end - begin; - - if (len > max) - panic("Exception code too big for vector %lx\n", addr); - - if (len == max) - printf("Exception vector at %lx has no more free space\n", addr); - memcpy((void *)addr, begin, len); -} - -/* r4000 exception handler address and end */ -extern char ExceptionVector[], ExceptionVectorEnd[]; - -/* TLB miss handler address and end */ -extern char TLBMissVector[], TLBMissVectorEnd[]; -extern char XTLBMissVector[], XTLBMissVectorEnd[]; - -/* Cache error handler */ -extern char CacheVector[], CacheVectorEnd[]; - -/* - * Do all the stuff that locore normally does before calling main(), - * that is common to all mips-CPU NetBSD ports. - * - * The principal purpose of this function is to examine the - * variable cpu_id, into which the kernel locore start code - * writes the cpu ID register, and to then copy appropriate - * code into the CPU exception-vector entries and the jump tables - * used to hide the differences in cache and TLB handling in - * different MIPS CPUs. - * - * This should be the very first thing called by each port's - * init_main() function. - */ - -/* - * Initialize the hardware exception vectors, and the jump table used to - * call locore cache and TLB management functions, based on the kind - * of CPU the kernel is running on. - */ -static void -mips_vector_init(void) -{ - const struct pridtab *ct; - - mycpu = NULL; - for (ct = cputab; ct->cpu_name != NULL; ct++) { - if (MIPS_PRID_CID(cpu_id) != ct->cpu_cid || - MIPS_PRID_IMPL(cpu_id) != ct->cpu_pid) - continue; - if (ct->cpu_rev >= 0 && - MIPS_PRID_REV(cpu_id) != ct->cpu_rev) - continue; - if (ct->cpu_copts >= 0 && - MIPS_PRID_COPTS(cpu_id) != ct->cpu_copts) - continue; - - mycpu = ct; - cpu_arch = ct->cpu_isa; - mips_num_tlb_entries = ct->cpu_ntlb; - break; - } - - if (mycpu == NULL) - panic("CPU type (0x%x) not supported", cpu_id); - - if (MIPS_PRID_CID(cpu_id) != 0) { - /* MIPS32/MIPS64, use coprocessor 0 config registers */ - uint32_t cfg, cfg1; - - cfg = mips_rd_config(); - cfg1 = mipsNN_cp0_config1_read(); - - /* pick CPU type */ - switch (MIPSNN_GET(CFG_AT, cfg)) { - case MIPSNN_CFG_AT_MIPS32: - cpu_arch = CPU_ARCH_MIPS32; - break; - case MIPSNN_CFG_AT_MIPS64: - cpu_arch = CPU_ARCH_MIPS64; - break; - case MIPSNN_CFG_AT_MIPS64S: - default: - panic("MIPS32/64 architecture type %d not supported", - MIPSNN_GET(CFG_AT, cfg)); - } - - if (MIPSNN_GET(CFG_AR, cfg) != MIPSNN_CFG_AR_REV1) - printf("WARNING: MIPS32/64 arch revision != revision 1!\n"); - - /* figure out MMU type (and number of TLB entries) */ - switch (MIPSNN_GET(CFG_MT, cfg)) { - case MIPSNN_CFG_MT_TLB: - mips_num_tlb_entries = MIPSNN_CFG1_MS(cfg1); - break; - case MIPSNN_CFG_MT_NONE: - case MIPSNN_CFG_MT_BAT: - case MIPSNN_CFG_MT_FIXED: - default: - panic("MIPS32/64 MMU type %d not supported", - MIPSNN_GET(CFG_MT, cfg)); - } - } - - if (cpu_arch < 1) - panic("Unknown CPU ISA for CPU type 0x%x", cpu_id); - if (mips_num_tlb_entries < 1) - panic("Unknown number of TLBs for CPU type 0x%x", cpu_id); - - /* - * Check cpu-specific flags. - */ - mips_cpu_flags = mycpu->cpu_flags; - mips_has_r4k_mmu = mips_cpu_flags & CPU_MIPS_R4K_MMU; - mips_has_llsc = (mips_cpu_flags & CPU_MIPS_NO_LLSC) == 0; - -#ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG - mips_machdep_cache_config(); -#endif - - /* - * Determine cache configuration and initialize our cache - * frobbing routine function pointers. - */ - mips_config_cache(); - - /* - * Now initialize our ISA-dependent function vector. - */ - switch (cpu_arch) { - case CPU_ARCH_MIPS3: - case CPU_ARCH_MIPS4: - case CPU_ARCH_MIPS64: - break; - default: - printf("cpu_arch 0x%x: not supported\n", cpu_arch); - cpu_halt(); - } - - tlb_invalidate_all(); - - /* - * Copy down exception vector code. - */ - - mips_vector_install(MIPS_UTLB_MISS_EXC_VEC, - TLBMissVector, TLBMissVectorEnd); - mips_vector_install(MIPS_XTLB_MISS_EXC_VEC, - XTLBMissVector, XTLBMissVectorEnd); - mips_vector_install(MIPS_CACHE_ERR_EXC_VEC, - CacheVector, CacheVectorEnd); - mips_vector_install(MIPS_GEN_EXC_VEC, - ExceptionVector, ExceptionVectorEnd); - /* XXX do a real interrupt vector for the mips32/64? */ - mips_vector_install(MIPS_INTR_EXC_VEC, - ExceptionVector, ExceptionVectorEnd); - - mips_icache_sync_all(); - mips_dcache_wbinv_all(); - - /* Clear BEV in SR so we start handling our own exceptions */ - mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV); -} - -/* - * Identify product revision IDs of cpu and fpu. - */ -static void -cpu_identify(void) -{ - static const char * const waynames[] = { - "fully set-associative", /* 0 */ - "direct-mapped", /* 1 */ - "2-way set-associative", /* 2 */ - NULL, /* 3 */ - "4-way set-associative", /* 4 */ - }; -#define nwaynames (sizeof(waynames) / sizeof(waynames[0])) - static const char * const wtnames[] = { - "write-back", - "write-through", - }; - static const char * const label = "cpu0"; /* XXX */ - char *cpuname, *fpuname; - int i; - - cpuname = mycpu->cpu_name; - - fpuname = NULL; - for (i = 0; i < sizeof(fputab)/sizeof(fputab[0]); i++) { - if (MIPS_PRID_CID(fpu_id) == fputab[i].cpu_cid && - MIPS_PRID_IMPL(fpu_id) == fputab[i].cpu_pid) { - fpuname = fputab[i].cpu_name; - break; - } - } - if (fpuname == NULL && MIPS_PRID_IMPL(fpu_id) == MIPS_PRID_IMPL(cpu_id)) - fpuname = "built-in FPU"; - if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4700) /* FPU PRid is 0x20 */ - fpuname = "built-in FPU"; - if (MIPS_PRID_IMPL(cpu_id) == MIPS_RC64470) /* FPU PRid is 0x21 */ - fpuname = "built-in FPU"; - - if (mycpu->cpu_cid != 0) { - if (mycpu->cpu_cid <= ncidnames) - printf("%s ", cidnames[mycpu->cpu_cid]); - else { - printf("Unknown Company ID - 0x%x", mycpu->cpu_cid); - printf("%s: ", label); >>> TRUNCATED FOR MAIL (1000 lines) <<<
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