Date: Sun, 28 Apr 2013 00:57:47 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r250008 - head/sys/contrib/dev/ath/ath_hal/ar9300 Message-ID: <201304280057.r3S0vlJp045085@svn.freebsd.org>
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Author: adrian Date: Sun Apr 28 00:57:47 2013 New Revision: 250008 URL: http://svnweb.freebsd.org/changeset/base/250008 Log: Bring over my FreeBSD modifications for the AR9300 HAL to make it work in FreeBSD. This is still heavily a work in progress but I'd rather it start shipping in -HEAD sooner rather than later. This doesn't (yet) link it into the build system either for a static kernel or as a module; that will come later (after many, many make universe tests.) Added: head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_devid.h head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_freebsd.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_freebsd.h head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_freebsd_inc.h head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_stub.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_stub.h head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_stub_funcs.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_stub_funcs.h Modified: head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300.h head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_ani.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_attach.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_beacon.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_eeprom.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_gpio.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_interrupts.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_keycache.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_mci.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_misc.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_paprd.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_phy.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_power.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_radar.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_radio.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_recv.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_recv_ds.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_reset.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_timer.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_xmit.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_xmit_ds.c head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300desc.h head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300eep.h head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300paprd.h Modified: head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300.h ============================================================================== --- head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300.h Sun Apr 28 00:53:31 2013 (r250007) +++ head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300.h Sun Apr 28 00:57:47 2013 (r250008) @@ -17,11 +17,31 @@ #ifndef _ATH_AR9300_H_ #define _ATH_AR9300_H_ +#include "ar9300_freebsd_inc.h" + +#define AH_BIG_ENDIAN 4321 +#define AH_LITTLE_ENDIAN 1234 + +#if _BYTE_ORDER == _BIG_ENDIAN +#define AH_BYTE_ORDER AH_BIG_ENDIAN +#else +#define AH_BYTE_ORDER AH_LITTLE_ENDIAN +#endif + +/* XXX doesn't belong here */ +#define AR_EEPROM_MODAL_SPURS 5 + +/* + * (a) this should be N(a), + * (b) FreeBSD does define nitems, + * (c) it doesn't have an AH_ prefix, sigh. + */ +#define ARRAY_LENGTH(a) (sizeof(a) / sizeof((a)[0])) + #include "ah_internal.h" #include "ah_eeprom.h" #include "ah_devid.h" #include "ar9300eep.h" /* For Eeprom definitions */ -#include "asf_amem.h" #define AR9300_MAGIC 0x19741014 @@ -117,9 +137,9 @@ typedef struct { /* RF HAL structures */ typedef struct rf_hal_funcs { - HAL_BOOL (*set_channel)(struct ath_hal *, HAL_CHANNEL_INTERNAL *); - HAL_BOOL (*get_chip_power_lim)(struct ath_hal *ah, HAL_CHANNEL *chans, - u_int32_t nchancs); + HAL_BOOL (*set_channel)(struct ath_hal *, struct ieee80211_channel *); + HAL_BOOL (*get_chip_power_lim)(struct ath_hal *ah, + struct ieee80211_channel *chan); } RF_HAL_FUNCS; struct ar9300_ani_default { @@ -143,7 +163,7 @@ struct ar9300_ani_default { * Per-channel ANI state private to the driver. */ struct ar9300_ani_state { - HAL_CHANNEL c; + struct ieee80211_channel c; /* XXX ew? */ HAL_BOOL must_restore; HAL_BOOL ofdms_turn; u_int8_t ofdm_noise_immunity_level; @@ -256,7 +276,7 @@ struct ar9300_ar_state { }; struct ar9300_radar_state { - HAL_CHANNEL_INTERNAL *rs_chan; /* Channel info */ + struct ieee80211_channel *rs_chan; /* Channel info */ u_int8_t rs_chan_index; /* Channel index in radar structure */ u_int32_t rs_num_radar_events; /* Number of radar events */ int32_t rs_firpwr; /* Thresh to check radar sig is gone */ @@ -380,9 +400,15 @@ struct ar9300_paprd_pwr_adjust { u_int32_t sub_db; // offset value unit of dB }; +struct ar9300NfLimits { + int16_t max; + int16_t min; + int16_t nominal; +}; + #define AR9300_MAX_RATES 36 /* legacy(4) + ofdm(8) + HTSS(8) + HTDS(8) + HTTS(8)*/ struct ath_hal_9300 { - struct ath_hal_private_tables ah_priv; /* base class */ + struct ath_hal_private ah_priv; /* base class */ /* * Information retrieved from EEPROM. @@ -582,6 +608,13 @@ struct ath_hal_9300 { /* bb hang detection */ int ah_hang[6]; hal_hw_hangs_t ah_hang_wars; + + /* + * Keytable type table + */ +#define AR_KEYTABLE_SIZE 128 /* XXX! */ + uint8_t ah_keytype[AR_KEYTABLE_SIZE]; +#undef AR_KEYTABLE_SIZE /* * Support for ar9300 multiple INIs */ @@ -647,7 +680,6 @@ struct ath_hal_9300 { /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains */ int16_t txpower[AR9300_MAX_RATES][AR9300_MAX_CHAINS]; - /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains with STBC*/ int16_t txpower_stbc[AR9300_MAX_RATES][AR9300_MAX_CHAINS]; @@ -819,7 +851,33 @@ struct ath_hal_9300 { u_int32_t ah_mcast_filter_l32_set; u_int32_t ah_mcast_filter_u32_set; #endif - HAL_BOOL ah_reduced_self_gen_mask; + HAL_BOOL ah_reduced_self_gen_mask; + + /* Local additions for FreeBSD */ + /* + * These fields are in the top level HAL in the atheros + * codebase; here we place them in the AR9300 HAL and + * access them via accessor methods if the driver requires them. + */ + u_int32_t ah_ob_db1[3]; + u_int32_t ah_db2[3]; + u_int32_t ah_bb_panic_timeout_ms; + u_int32_t ah_bb_panic_last_status; + u_int32_t ah_tx_trig_level; + u_int16_t ath_hal_spur_chans[AR_EEPROM_MODAL_SPURS][2]; + int16_t nf_cw_int_delta; /* diff btwn nominal NF and CW interf threshold */ + int ah_phyrestart_disabled; + HAL_RSSI_TX_POWER green_tx_status; + int green_ap_ps_on; + int ah_enable_keysearch_always; + int ah_fccaifs; + int ah_reset_reason; + int ah_dcs_enable; + + struct ar9300NfLimits nf_2GHz; + struct ar9300NfLimits nf_5GHz; + struct ar9300NfLimits *nfp; + }; #define AH9300(_ah) ((struct ath_hal_9300 *)(_ah)) @@ -830,11 +888,7 @@ struct ath_hal_9300 { #define ar9300_eep_data_in_flash(_ah) \ (!(AH_PRIVATE(_ah)->ah_flags & AH_USE_EEPROM)) -#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ - (IS_CHAN_5GHZ(_c) && \ - ((AH_PRIVATE(_ah))->ah_config.ath_hal_fastClockEnable)) - -#if notyet +#ifdef notyet // Need these additional conditions for IS_5GHZ_FAST_CLOCK_EN when we have valid eeprom contents. && \ ((ar9300_eeprom_get(AH9300(_ah), EEP_MINOR_REV) <= AR9300_EEP_MINOR_VER_16) || \ @@ -880,9 +934,6 @@ struct ath_hal_9300 { " not supported but called from %s\n", (func)) #endif /* AH_ASSERT */ -extern void ar9300_detach(struct ath_hal *ah); -extern void ar9300_get_desc_info(struct ath_hal *ah, HAL_DESC_INFO *desc_info); - /* * Green Tx, Based on different RSSI of Received Beacon thresholds, * using different tx power by modified register tx power related values. @@ -1129,15 +1180,10 @@ extern HAL_BOOL ar9300_rf_attach(struct struct ath_hal; extern struct ath_hal_9300 * ar9300_new_state(u_int16_t devid, - HAL_ADAPTER_HANDLE osdev, HAL_SOFTC sc, - HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_BUS_TYPE bustype, - asf_amem_instance_handle amem_handle, - struct hal_reg_parm *hal_conf_parm, HAL_STATUS *status); + HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, + HAL_STATUS *status); extern struct ath_hal * ar9300_attach(u_int16_t devid, - HAL_ADAPTER_HANDLE osdev, HAL_SOFTC sc, - HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_BUS_TYPE bustype, - asf_amem_instance_handle amem_handle, - struct hal_reg_parm *hal_conf_parm, + HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_STATUS *status); extern void ar9300_detach(struct ath_hal *ah); extern void ar9300_read_revisions(struct ath_hal *ah); @@ -1162,6 +1208,9 @@ extern u_int32_t ar9300_get_intr_mitiga extern u_int32_t ar9300_get_key_cache_size(struct ath_hal *); extern HAL_BOOL ar9300_is_key_cache_entry_valid(struct ath_hal *, u_int16_t entry); extern HAL_BOOL ar9300_reset_key_cache_entry(struct ath_hal *ah, u_int16_t entry); +extern HAL_CHANNEL_INTERNAL * ar9300_check_chan(struct ath_hal *ah, + const struct ieee80211_channel *chan); + extern HAL_BOOL ar9300_set_key_cache_entry_mac(struct ath_hal *, u_int16_t entry, const u_int8_t *mac); extern HAL_BOOL ar9300_set_key_cache_entry(struct ath_hal *ah, u_int16_t entry, @@ -1173,13 +1222,12 @@ extern HAL_BOOL ar9300_set_mac_address( extern void ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mac); extern HAL_BOOL ar9300_set_bss_id_mask(struct ath_hal *, const u_int8_t *); extern HAL_STATUS ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg); -extern u_int32_t ar9300_ant_ctrl_common_get(struct ath_hal *ah, HAL_BOOL is_2ghz); extern HAL_BOOL ar9300_set_regulatory_domain(struct ath_hal *ah, u_int16_t reg_domain, HAL_STATUS *stats); extern u_int ar9300_get_wireless_modes(struct ath_hal *ah); extern void ar9300_enable_rf_kill(struct ath_hal *); -extern HAL_BOOL ar9300_gpio_cfg_output(struct ath_hal *, u_int32_t gpio, HAL_GPIO_OUTPUT_MUX_TYPE signalType); -extern HAL_BOOL ar9300_gpio_cfg_output_led_off(struct ath_hal *, u_int32_t gpio, HAL_GPIO_OUTPUT_MUX_TYPE signalType); +extern HAL_BOOL ar9300_gpio_cfg_output(struct ath_hal *, u_int32_t gpio, HAL_GPIO_MUX_TYPE signalType); +extern HAL_BOOL ar9300_gpio_cfg_output_led_off(struct ath_hal *, u_int32_t gpio, HAL_GPIO_MUX_TYPE signalType); extern HAL_BOOL ar9300_gpio_cfg_input(struct ath_hal *, u_int32_t gpio); extern HAL_BOOL ar9300_gpio_set(struct ath_hal *, u_int32_t gpio, u_int32_t val); extern u_int32_t ar9300_gpio_get(struct ath_hal *ah, u_int32_t gpio); @@ -1200,7 +1248,6 @@ extern int ar9300_ppm_get_trigger(struc extern u_int32_t ar9300_ppm_force(struct ath_hal *); extern void ar9300_ppm_un_force(struct ath_hal *); extern u_int32_t ar9300_ppm_get_force_state(struct ath_hal *); -extern u_int32_t ar9300_ppm_get_force_state(struct ath_hal *); extern void ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t); extern u_int32_t ar9300_get_dcs_mode(struct ath_hal *ah); extern u_int32_t ar9300_get_tsf32(struct ath_hal *ah); @@ -1219,7 +1266,8 @@ extern u_int32_t ar9300_get_rssi_chain0 extern u_int ar9300_get_def_antenna(struct ath_hal *ah); extern void ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna); extern HAL_BOOL ar9300_set_antenna_switch(struct ath_hal *ah, - HAL_ANT_SETTING settings, HAL_CHANNEL *chan, u_int8_t *, u_int8_t *, u_int8_t *); + HAL_ANT_SETTING settings, const struct ieee80211_channel *chan, + u_int8_t *, u_int8_t *, u_int8_t *); extern HAL_BOOL ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah); extern HAL_BOOL ar9300_set_slot_time(struct ath_hal *, u_int); extern HAL_BOOL ar9300_set_ack_timeout(struct ath_hal *, u_int); @@ -1235,7 +1283,7 @@ extern HAL_BOOL ar9300_get_diag_state(s const void *args, u_int32_t argsize, void **result, u_int32_t *resultsize); extern void ar9300_get_desc_info(struct ath_hal *ah, HAL_DESC_INFO *desc_info); -extern int8_t ar9300_get_11n_ext_busy(struct ath_hal *ah); +extern uint32_t ar9300_get_11n_ext_busy(struct ath_hal *ah); extern void ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode); extern HAL_HT_RXCLEAR ar9300_get_11n_rx_clear(struct ath_hal *ah); extern void ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear); @@ -1256,7 +1304,7 @@ extern void ar9300_wow_apply_pattern(st u_int8_t *p_ath_mask, int32_t pattern_count, u_int32_t ath_pattern_len); //extern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah,u_int8_t *chipPatternBytes); extern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah, HAL_BOOL offloadEnable); -extern HAL_BOOL ar9300_wow_enable(struct ath_hal *ah, u_int32_t pattern_enable, u_int32_t timeout_in_seconds, int clearbssid, +extern bool ar9300_wow_enable(struct ath_hal *ah, u_int32_t pattern_enable, u_int32_t timeout_in_seconds, int clearbssid, HAL_BOOL offloadEnable); #if ATH_WOW_OFFLOAD /* ARP offload */ @@ -1318,24 +1366,25 @@ extern void ar9300_wowoffload_download_ #endif /* ATH_WOW_OFFLOAD */ #endif -extern HAL_BOOL ar9300_reset(struct ath_hal *ah, HAL_OPMODE opmode, - HAL_CHANNEL *chan, HAL_HT_MACMODE macmode, u_int8_t txchainmask, +extern HAL_BOOL ar9300_reset(struct ath_hal *ah, HAL_OPMODE opmode, + struct ieee80211_channel *chan, HAL_HT_MACMODE macmode, u_int8_t txchainmask, u_int8_t rxchainmask, HAL_HT_EXTPROTSPACING extprotspacing, HAL_BOOL b_channel_change, HAL_STATUS *status, int is_scan); -extern HAL_BOOL ar9300_lean_channel_change(struct ath_hal *ah, HAL_OPMODE opmode, HAL_CHANNEL *chan, +extern HAL_BOOL ar9300_lean_channel_change(struct ath_hal *ah, HAL_OPMODE opmode, struct ieee80211_channel *chan, HAL_HT_MACMODE macmode, u_int8_t txchainmask, u_int8_t rxchainmask); extern HAL_BOOL ar9300_set_reset_reg(struct ath_hal *ah, u_int32_t type); -extern void ar9300_init_pll(struct ath_hal *ah, HAL_CHANNEL *chan); +extern void ar9300_init_pll(struct ath_hal *ah, struct ieee80211_channel *chan); extern void ar9300_green_ap_ps_on_off( struct ath_hal *ah, u_int16_t rxMask); extern u_int16_t ar9300_is_single_ant_power_save_possible(struct ath_hal *ah); extern void ar9300_set_operating_mode(struct ath_hal *ah, int opmode); extern HAL_BOOL ar9300_phy_disable(struct ath_hal *ah); extern HAL_BOOL ar9300_disable(struct ath_hal *ah); -extern HAL_BOOL ar9300_chip_reset(struct ath_hal *ah, HAL_CHANNEL *); -extern HAL_BOOL ar9300_calibration(struct ath_hal *ah, HAL_CHANNEL *chan, +extern HAL_BOOL ar9300_chip_reset(struct ath_hal *ah, struct ieee80211_channel *); +extern HAL_BOOL ar9300_calibration(struct ath_hal *ah, struct ieee80211_channel *chan, u_int8_t rxchainmask, HAL_BOOL longcal, HAL_BOOL *isIQdone, int is_scan, u_int32_t *sched_cals); -extern void ar9300_reset_cal_valid(struct ath_hal *ah, HAL_CHANNEL *chan, - HAL_BOOL *isIQdone, u_int32_t cal_type); +extern void ar9300_reset_cal_valid(struct ath_hal *ah, + const struct ieee80211_channel *chan, + HAL_BOOL *isIQdone, u_int32_t cal_type); extern void ar9300_iq_cal_collect(struct ath_hal *ah, u_int8_t num_chains); extern void ar9300_iq_calibration(struct ath_hal *ah, u_int8_t num_chains); extern void ar9300_temp_comp_cal_collect(struct ath_hal *ah); @@ -1346,7 +1395,7 @@ extern void ar9300_upload_noise_floor(st extern HAL_BOOL ar9300_set_tx_power_limit(struct ath_hal *ah, u_int32_t limit, u_int16_t extra_txpow, u_int16_t tpc_in_db); extern void ar9300_chain_noise_floor(struct ath_hal *ah, int16_t *nf_buf, - HAL_CHANNEL *chan, int is_scan); + struct ieee80211_channel *chan, int is_scan); extern HAL_BOOL ar9300_load_nf(struct ath_hal *ah, int16_t nf[]); extern HAL_RFGAIN ar9300_get_rfgain(struct ath_hal *ah); @@ -1354,11 +1403,14 @@ extern const HAL_RATE_TABLE *ar9300_get_ extern int16_t ar9300_get_rate_txpower(struct ath_hal *ah, u_int mode, u_int8_t rate_index, u_int8_t chainmask, u_int8_t mimo_mode); extern void ar9300_init_rate_txpower(struct ath_hal *ah, u_int mode, - HAL_CHANNEL_INTERNAL *chan, + const struct ieee80211_channel *chan, u_int8_t powerPerRate[], u_int8_t chainmask); extern void ar9300_adjust_reg_txpower_cdd(struct ath_hal *ah, u_int8_t powerPerRate[]); +extern HAL_STATUS ath_hal_get_rate_power_limit_from_eeprom(struct ath_hal *ah, + u_int16_t freq, int8_t *max_rate_power, int8_t *min_rate_power); + extern void ar9300_reset_tx_status_ring(struct ath_hal *ah); extern void ar9300_enable_mib_counters(struct ath_hal *); extern void ar9300_disable_mib_counters(struct ath_hal *); @@ -1371,7 +1423,7 @@ struct ath_rx_status; extern void ar9300_process_mib_intr(struct ath_hal *, const HAL_NODE_STATS *); extern void ar9300_ani_ar_poll(struct ath_hal *, const HAL_NODE_STATS *, - HAL_CHANNEL *, HAL_ANISTATS *); + const struct ieee80211_channel *, HAL_ANISTATS *); extern void ar9300_ani_reset(struct ath_hal *, HAL_BOOL is_scanning); extern void ar9300_ani_init_defaults(struct ath_hal *ah, HAL_HT_MACMODE macmode); extern void ar9300_enable_tpc(struct ath_hal *); @@ -1381,9 +1433,8 @@ extern void ar9300_rx_gain_table_apply(s extern void ar9300_tx_gain_table_apply(struct ath_hal *ah); extern void ar9300_mat_enable(struct ath_hal *ah, int enable); extern void ar9300_dump_keycache(struct ath_hal *ah, int n, u_int32_t *entry); -extern HAL_BOOL ar9300_ant_ctrl_set_lna_div_use_bt_ant(struct ath_hal * ah, HAL_BOOL enable, HAL_CHANNEL * chan); +extern HAL_BOOL ar9300_ant_ctrl_set_lna_div_use_bt_ant(struct ath_hal * ah, HAL_BOOL enable, const struct ieee80211_channel * chan); -#ifdef AH_SUPPORT_AR9300 /* BB Panic Watchdog declarations */ #define HAL_BB_PANIC_WD_TMO 25 /* in ms, 0 to disable */ #define HAL_BB_PANIC_WD_TMO_HORNET 85 @@ -1391,17 +1442,15 @@ extern void ar9300_config_bb_panic_watch extern void ar9300_handle_bb_panic(struct ath_hal *); extern int ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic); extern HAL_BOOL ar9300_handle_radar_bb_panic(struct ath_hal *ah); -#endif extern void ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason); /* DFS declarations */ -#ifdef ATH_SUPPORT_DFS -extern void ar9300_check_dfs(struct ath_hal *ah, HAL_CHANNEL *chan); -extern void ar9300_dfs_found(struct ath_hal *ah, HAL_CHANNEL *chan, +extern void ar9300_check_dfs(struct ath_hal *ah, struct ieee80211_channel *chan); +extern void ar9300_dfs_found(struct ath_hal *ah, struct ieee80211_channel *chan, u_int64_t nolTime); extern void ar9300_enable_dfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); extern void ar9300_get_dfs_thresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); -extern HAL_BOOL ar9300_radar_wait(struct ath_hal *ah, HAL_CHANNEL *chan); +extern HAL_BOOL ar9300_radar_wait(struct ath_hal *ah, struct ieee80211_channel *chan); extern struct dfs_pulse * ar9300_get_dfs_radars(struct ath_hal *ah, u_int32_t dfsdomain, int *numradars, struct dfs_bin5pulse **bin5pulses, int *numb5radars, HAL_PHYERR_PARAM *pe); @@ -1409,9 +1458,8 @@ extern void ar9300_adjust_difs(struct a extern u_int32_t ar9300_dfs_config_fft(struct ath_hal *ah, HAL_BOOL is_enable); extern void ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable); extern void ar9300_dfs_cac_war(struct ath_hal *ah, u_int32_t start); -#endif -extern HAL_CHANNEL * ar9300_get_extension_channel(struct ath_hal *ah); +extern struct ieee80211_channel * ar9300_get_extension_channel(struct ath_hal *ah); extern HAL_BOOL ar9300_is_fast_clock_enabled(struct ath_hal *ah); @@ -1440,16 +1488,16 @@ extern HAL_STATUS ar9300_calc_adc_ref_po extern HAL_STATUS ar9300_get_min_agc_gain(struct ath_hal *ah, int freq_mhz, int32_t *chain_gain, int num_chain_gain); extern HAL_BOOL ar9300_reset_11n(struct ath_hal *ah, HAL_OPMODE opmode, - HAL_CHANNEL *chan, HAL_BOOL b_channel_change, HAL_STATUS *status); + struct ieee80211_channel *chan, HAL_BOOL b_channel_change, HAL_STATUS *status); extern void ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now); extern void ar9300_get_channel_centers(struct ath_hal *ah, - HAL_CHANNEL_INTERNAL *chan, + const struct ieee80211_channel *chan, CHAN_CENTERS *centers); extern u_int16_t ar9300_get_ctl_center(struct ath_hal *ah, - HAL_CHANNEL_INTERNAL *chan); + const struct ieee80211_channel *chan); extern u_int16_t ar9300_get_ext_center(struct ath_hal *ah, - HAL_CHANNEL_INTERNAL *chan); + const struct ieee80211_channel *chan); extern u_int32_t ar9300_get_mib_cycle_counts_pct(struct ath_hal *, u_int32_t*, u_int32_t*, u_int32_t*); extern void ar9300_dma_reg_dump(struct ath_hal *); @@ -1485,20 +1533,20 @@ extern void ar9300_chk_rssi_update_tx_pw extern HAL_BOOL ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah); extern void ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah); extern void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value); +extern HAL_BOOL ar9300_is_ani_noise_spur(struct ath_hal *ah); extern void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah); extern int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah); extern void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah, u_int32_t rssi_threshold); extern void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah); extern void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on); -extern HAL_BOOL ar9300_is_ani_noise_spur(struct ath_hal *ah); extern void ar9300_get_vow_stats(struct ath_hal *ah, HAL_VOWSTATS *p_stats, u_int8_t); extern int ar9300_get_spur_info(struct ath_hal * ah, int *enable, int len, u_int16_t *freq); extern int ar9300_set_spur_info(struct ath_hal * ah, int enable, int len, u_int16_t *freq); extern void ar9300_wow_set_gpio_reset_low(struct ath_hal * ah); -extern void ar9300_get_mib_cycle_counts(struct ath_hal *, HAL_COUNTERS*); +extern HAL_BOOL ar9300_get_mib_cycle_counts(struct ath_hal *, HAL_SURVEY_SAMPLE *); extern void ar9300_clear_mib_counters(struct ath_hal *ah); /* EEPROM interface functions */ @@ -1512,12 +1560,12 @@ extern u_int32_t ar9300_ini_fixup(struc u_int32_t val); extern HAL_STATUS ar9300_eeprom_set_transmit_power(struct ath_hal *ah, - ar9300_eeprom_t *p_eep_data, HAL_CHANNEL_INTERNAL *chan, + ar9300_eeprom_t *p_eep_data, const struct ieee80211_channel *chan, u_int16_t cfg_ctl, u_int16_t twice_antenna_reduction, u_int16_t twice_max_regulatory_power, u_int16_t power_limit); -extern void ar9300_eeprom_set_addac(struct ath_hal *, HAL_CHANNEL_INTERNAL *); +extern void ar9300_eeprom_set_addac(struct ath_hal *, struct ieee80211_channel *); extern HAL_BOOL ar9300_eeprom_set_param(struct ath_hal *ah, EEPROM_PARAM param, u_int32_t value); -extern HAL_BOOL ar9300_eeprom_set_board_values(struct ath_hal *, HAL_CHANNEL_INTERNAL *); +extern HAL_BOOL ar9300_eeprom_set_board_values(struct ath_hal *, const struct ieee80211_channel *); extern HAL_BOOL ar9300_eeprom_read_word(struct ath_hal *, u_int off, u_int16_t *data); extern HAL_BOOL ar9300_eeprom_read(struct ath_hal *ah, long address, u_int8_t *buffer, int many); extern HAL_BOOL ar9300_otp_read(struct ath_hal *ah, u_int off, u_int32_t *data, HAL_BOOL is_wifi); @@ -1526,7 +1574,7 @@ extern HAL_BOOL ar9300_flash_read(struc extern HAL_BOOL ar9300_flash_write(struct ath_hal *, u_int off, u_int16_t data); extern u_int ar9300_eeprom_dump_support(struct ath_hal *ah, void **pp_e); extern u_int8_t ar9300_eeprom_get_num_ant_config(struct ath_hal_9300 *ahp, HAL_FREQ_BAND freq_band); -extern HAL_STATUS ar9300_eeprom_get_ant_cfg(struct ath_hal_9300 *ahp, HAL_CHANNEL_INTERNAL *chan, +extern HAL_STATUS ar9300_eeprom_get_ant_cfg(struct ath_hal_9300 *ahp, const struct ieee80211_channel *chan, u_int8_t index, u_int16_t *config); extern u_int8_t* ar9300_eeprom_get_cust_data(struct ath_hal_9300 *ahp); extern u_int8_t *ar9300_eeprom_get_spur_chans_ptr(struct ath_hal *ah, HAL_BOOL is_2ghz); @@ -1625,7 +1673,7 @@ extern HAL_BOOL ar9300Get3StreamSignatur #ifdef ATH_TX99_DIAG #ifndef ATH_SUPPORT_HTC -extern void ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c, u_int32_t txpower); +extern void ar9300_tx99_channel_pwr_update(struct ath_hal *ah, struct ieee80211_channel *c, u_int32_t txpower); extern void ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask); extern void ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, int chtype); extern void ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data); Modified: head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_ani.c ============================================================================== --- head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_ani.c Sun Apr 28 00:53:31 2013 (r250007) +++ head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_ani.c Sun Apr 28 00:57:47 2013 (r250008) @@ -16,12 +16,10 @@ #include "opt_ah.h" -#ifdef AH_SUPPORT_AR9300 - #include "ah.h" #include "ah_internal.h" #include "ah_desc.h" -#include "ah_pktlog.h" +//#include "ah_pktlog.h" #include "ar9300/ar9300.h" #include "ar9300/ar9300reg.h" @@ -30,7 +28,7 @@ extern void ar9300_set_rx_filter(struct ath_hal *ah, u_int32_t bits); extern u_int32_t ar9300_get_rx_filter(struct ath_hal *ah); -#define HAL_ANI_DEBUG 0 +#define HAL_ANI_DEBUG 1 /* * Anti noise immunity support. We track phy errors and react @@ -47,7 +45,7 @@ extern u_int32_t ar9300_get_rx_filter(s #define HAL_ANI_OFDM_TRIG_LOW 400 /* units are errors per second */ #define HAL_ANI_CCK_TRIG_HIGH 600 /* units are errors per second */ #define HAL_ANI_CCK_TRIG_LOW 300 /* units are errors per second */ -#define HAL_ANI_USE_OFDM_WEAK_SIG true +#define HAL_ANI_USE_OFDM_WEAK_SIG AH_TRUE #define HAL_ANI_ENABLE_MRC_CCK AH_TRUE /* default is enabled */ #define HAL_ANI_DEF_SPUR_IMMUNE_LVL 3 #define HAL_ANI_DEF_FIRSTEP_LVL 2 @@ -177,18 +175,20 @@ ar9300_disable_mib_counters(struct ath_h * ah_ani values and only the channel field needs to be set. */ static int -ar9300_get_ani_channel_index(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan) +ar9300_get_ani_channel_index(struct ath_hal *ah, + const struct ieee80211_channel *chan) { struct ath_hal_9300 *ahp = AH9300(ah); int i; for (i = 0; i < ARRAY_LENGTH(ahp->ah_ani); i++) { - if (ahp->ah_ani[i].c.channel == chan->channel) { + /* XXX this doesn't distinguish between 20/40 channels */ + if (ahp->ah_ani[i].c.ic_freq == chan->ic_freq) { return i; } - if (ahp->ah_ani[i].c.channel == 0) { - ahp->ah_ani[i].c.channel = chan->channel; - ahp->ah_ani[i].c.channel_flags = chan->channel_flags; + if (ahp->ah_ani[i].c.ic_freq == 0) { + ahp->ah_ani[i].c.ic_freq = chan->ic_freq; + ahp->ah_ani[i].c.ic_flags = chan->ic_flags; return i; } } @@ -268,7 +268,7 @@ ar9300_ani_attach(struct ath_hal *ah) ar9300_enable_mib_counters(ah); ahp->ah_ani_period = HAL_ANI_PERIOD; - if (AH_PRIVATE(ah)->ah_config.ath_hal_enable_ani) { + if (ah->ah_config.ath_hal_enable_ani) { ahp->ah_proc_phy_err |= HAL_PROCESS_ANI; } } @@ -295,7 +295,7 @@ ar9300_ani_init_defaults(struct ath_hal { struct ath_hal_9300 *ahp = AH9300(ah); struct ar9300_ani_state *ani_state; - HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; + const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; int index; u_int32_t val; @@ -307,7 +307,7 @@ ar9300_ani_init_defaults(struct ath_hal HALDEBUG(ah, HAL_DEBUG_ANI, "%s: ver %d.%d opmode %u chan %d Mhz/0x%x macmode %d\n", __func__, AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev, - AH_PRIVATE(ah)->ah_opmode, chan->channel, chan->channel_flags, macmode); + AH_PRIVATE(ah)->ah_opmode, chan->ic_freq, chan->ic_flags, macmode); val = OS_REG_READ(ah, AR_PHY_SFCORR); ani_state->ini_def.m1_thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); @@ -457,16 +457,16 @@ ar9300_ani_control(struct ath_hal *ah, H { struct ath_hal_9300 *ahp = AH9300(ah); struct ar9300_ani_state *ani_state = ahp->ah_curani; - HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; + const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; int32_t value, value2; u_int level = param; u_int is_on; - if (chan == NULL && cmd != HAL_ANI_MODE) { - HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, + if (chan == NULL && cmd != HAL_ANI_MODE) { + HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: ignoring cmd 0x%02x - no channel\n", __func__, cmd); - return AH_FALSE; - } + return AH_FALSE; + } switch (cmd & ahp->ah_ani_function) { case HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION: @@ -538,7 +538,7 @@ ar9300_ani_control(struct ath_hal *ah, H if (!is_on != ani_state->ofdm_weak_sig_detect_off) { HALDEBUG(ah, HAL_DEBUG_ANI, "%s: ** ch %d: ofdm weak signal: %s=>%s\n", - __func__, chan->channel, + __func__, chan->ic_freq, !ani_state->ofdm_weak_sig_detect_off ? "on" : "off", is_on ? "on" : "off"); if (is_on) { @@ -592,12 +592,12 @@ ar9300_ani_control(struct ath_hal *ah, H if (level != ani_state->firstep_level) { HALDEBUG(ah, HAL_DEBUG_ANI, "%s: ** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", - __func__, chan->channel, ani_state->firstep_level, level, + __func__, chan->ic_freq, ani_state->firstep_level, level, HAL_ANI_DEF_FIRSTEP_LVL, value, ani_state->ini_def.firstep); HALDEBUG(ah, HAL_DEBUG_ANI, "%s: ** ch %d: level %d=>%d[def:%d] " "firstep_low[level]=%d ini=%d\n", - __func__, chan->channel, ani_state->firstep_level, level, + __func__, chan->ic_freq, ani_state->firstep_level, level, HAL_ANI_DEF_FIRSTEP_LVL, value2, ani_state->ini_def.firstep_low); if (level > ani_state->firstep_level) { @@ -651,13 +651,13 @@ ar9300_ani_control(struct ath_hal *ah, H HALDEBUG(ah, HAL_DEBUG_ANI, "%s: ** ch %d: level %d=>%d[def:%d] " "cycpwr_thr1[level]=%d ini=%d\n", - __func__, chan->channel, ani_state->spur_immunity_level, level, + __func__, chan->ic_freq, ani_state->spur_immunity_level, level, HAL_ANI_DEF_SPUR_IMMUNE_LVL, value, ani_state->ini_def.cycpwr_thr1); HALDEBUG(ah, HAL_DEBUG_ANI, "%s: ** ch %d: level %d=>%d[def:%d] " "cycpwr_thr1_ext[level]=%d ini=%d\n", - __func__, chan->channel, ani_state->spur_immunity_level, level, + __func__, chan->ic_freq, ani_state->spur_immunity_level, level, HAL_ANI_DEF_SPUR_IMMUNE_LVL, value2, ani_state->ini_def.cycpwr_thr1_ext); if (level > ani_state->spur_immunity_level) { @@ -682,7 +682,7 @@ ar9300_ani_control(struct ath_hal *ah, H } if (!is_on != ani_state->mrc_cck_off) { HALDEBUG(ah, HAL_DEBUG_ANI, - "%s: ** ch %d: MRC CCK: %s=>%s\n", __func__, chan->channel, + "%s: ** ch %d: MRC CCK: %s=>%s\n", __func__, chan->ic_freq, !ani_state->mrc_cck_off ? "on" : "off", is_on ? "on" : "off"); if (is_on) { ahp->ah_stats.ast_ani_ccklow++; @@ -857,7 +857,8 @@ ar9300_ani_reset(struct ath_hal *ah, HAL { struct ath_hal_9300 *ahp = AH9300(ah); struct ar9300_ani_state *ani_state; - HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; + const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; + HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); int index; HALASSERT(chan != AH_NULL); @@ -881,7 +882,7 @@ ar9300_ani_reset(struct ath_hal *ah, HAL /* only allow a subset of functions in AP mode */ if (AH_PRIVATE(ah)->ah_opmode == HAL_M_HOSTAP) { - if (IS_CHAN_2GHZ(chan)) { + if (IS_CHAN_2GHZ(ichan)) { ahp->ah_ani_function = (HAL_ANI_SPUR_IMMUNITY_LEVEL | HAL_ANI_FIRSTEP_LEVEL | HAL_ANI_MRC_CCK); @@ -908,8 +909,8 @@ ar9300_ani_reset(struct ath_hal *ah, HAL HALDEBUG(ah, HAL_DEBUG_ANI, "%s: Restore defaults: opmode %u chan %d Mhz/0x%x " "is_scanning=%d restore=%d ofdm:%d cck:%d\n", - __func__, AH_PRIVATE(ah)->ah_opmode, chan->channel, - chan->channel_flags, is_scanning, ani_state->must_restore, + __func__, AH_PRIVATE(ah)->ah_opmode, chan->ic_freq, + chan->ic_flags, is_scanning, ani_state->must_restore, ani_state->ofdm_noise_immunity_level, ani_state->cck_noise_immunity_level); /* @@ -941,8 +942,8 @@ ar9300_ani_reset(struct ath_hal *ah, HAL HALDEBUG(ah, HAL_DEBUG_ANI, "%s: Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d " "restore=%d ofdm:%d cck:%d\n", - __func__, AH_PRIVATE(ah)->ah_opmode, chan->channel, - chan->channel_flags, is_scanning, ani_state->must_restore, + __func__, AH_PRIVATE(ah)->ah_opmode, chan->ic_freq, + chan->ic_flags, is_scanning, ani_state->must_restore, ani_state->ofdm_noise_immunity_level, ani_state->cck_noise_immunity_level); ar9300_ani_set_odfm_noise_immunity_level( @@ -1041,7 +1042,8 @@ ar9300_ani_lower_immunity(struct ath_hal } /* convert HW counter values to ms using mode specifix clock rate */ -#define CLOCK_RATE(_ah) (ath_hal_chan_2_clock_rate_mhz(_ah) * 1000) +//#define CLOCK_RATE(_ah) (ath_hal_chan_2_clock_rate_mhz(_ah) * 1000) +#define CLOCK_RATE(_ah) (ath_hal_mac_clks(ah, 1000)) /* * Return an approximation of the time spent ``listening'' by @@ -1098,7 +1100,7 @@ ar9300_ani_get_listen_time(struct ath_ha */ void ar9300_ani_ar_poll(struct ath_hal *ah, const HAL_NODE_STATS *stats, - HAL_CHANNEL *chan, HAL_ANISTATS *ani_stats) + const struct ieee80211_channel *chan, HAL_ANISTATS *ani_stats) { struct ath_hal_9300 *ahp = AH9300(ah); struct ar9300_ani_state *ani_state; @@ -1274,4 +1276,3 @@ ar9300_is_ani_noise_spur(struct ath_hal return ani_state->phy_noise_spur; } -#endif /* AH_SUPPORT_AR9300 */ Modified: head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_attach.c ============================================================================== --- head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_attach.c Sun Apr 28 00:53:31 2013 (r250007) +++ head/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_attach.c Sun Apr 28 00:57:47 2013 (r250008) @@ -16,8 +16,6 @@ #include "opt_ah.h" -#ifdef AH_SUPPORT_AR9300 - #include "ah.h" #include "ah_internal.h" #include "ah_devid.h" @@ -28,6 +26,9 @@ #include "ar9300/ar9300phy.h" #include "ar9300/ar9300paprd.h" +#include "ar9300/ar9300_stub.h" +#include "ar9300/ar9300_stub_funcs.h" + /* Add static register initialization vectors */ #include "ar9300/ar9300_osprey22.ini" @@ -43,16 +44,23 @@ #include "ar9300/ar9300_aphrodite10.ini" +/* Include various freebsd specific HAL methods */ +#include "ar9300/ar9300_freebsd.h" + +/* XXX duplicate in ar9300_radio.c ? */ static HAL_BOOL ar9300_get_chip_power_limits(struct ath_hal *ah, - HAL_CHANNEL *chans, u_int32_t nchans); + struct ieee80211_channel *chan); static inline HAL_STATUS ar9300_init_mac_addr(struct ath_hal *ah); static inline HAL_STATUS ar9300_hw_attach(struct ath_hal *ah); static inline void ar9300_hw_detach(struct ath_hal *ah); static int16_t ar9300_get_nf_adjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c); +#if 0 int ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp, HAL_CAL_QUERY query); +#endif + #if ATH_TRAFFIC_FAST_RECOVER unsigned long ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah); #endif @@ -69,6 +77,7 @@ static const HAL_PERCAL_DATA iq_cal_sing ar9300_iq_cal_collect, ar9300_iq_calibration}; +#if 0 static HAL_CALIBRATION_TIMER ar9300_cals[] = { {IQ_MISMATCH_CAL, /* Cal type */ 1200000, /* Cal interval */ @@ -79,7 +88,8 @@ static HAL_CALIBRATION_TIMER ar9300_cals 0 }, }; - +#endif + #if ATH_PCIE_ERROR_MONITOR int ar9300_start_pcie_error_monitor(struct ath_hal *ah, int b_auto_stop) @@ -162,6 +172,7 @@ int ar9300_stop_pcie_error_monitor(struc #endif /* ATH_PCIE_ERROR_MONITOR */ +#if 0 /* WIN32 does not support C99 */ static const struct ath_hal_private ar9300hal = { { @@ -526,6 +537,7 @@ static const struct ath_hal_private ar93 ar9300_get_nf_adjust, /* ah_get_nf_adjust */ /* rest is zero'd by compiler */ }; +#endif /* * Read MAC version/revision information from Chip registers and initialize @@ -543,7 +555,7 @@ ar9300_read_revisions(struct ath_hal *ah if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9340) { /* XXX: AR_SREV register in Wasp reads 0 */ AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_WASP; - } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR955X) { + } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA955X) { /* XXX: AR_SREV register in Scorpion reads 0 */ AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_SCORPION; } else { @@ -592,10 +604,10 @@ ar9300_read_revisions(struct ath_hal *ah AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2); if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { - AH_PRIVATE(ah)->ah_is_pci_express = AH_TRUE; + AH_PRIVATE(ah)->ah_ispcie = AH_TRUE; } else { - AH_PRIVATE(ah)->ah_is_pci_express = + AH_PRIVATE(ah)->ah_ispcie = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; } @@ -605,39 +617,47 @@ ar9300_read_revisions(struct ath_hal *ah * Attach for an AR9300 part. */ struct ath_hal * -ar9300_attach(u_int16_t devid, HAL_ADAPTER_HANDLE osdev, HAL_SOFTC sc, - HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_BUS_TYPE bustype, - asf_amem_instance_handle amem_handle, - struct hal_reg_parm *hal_conf_parm, HAL_STATUS *status) +ar9300_attach(u_int16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st, + HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_STATUS *status) { struct ath_hal_9300 *ahp; struct ath_hal *ah; struct ath_hal_private *ahpriv; HAL_STATUS ecode; - HAL_NO_INTERSPERSED_READS; + HAL_NO_INTERSPERSED_READS; /* NB: memory is returned zero'd */ - ahp = ar9300_new_state( - devid, osdev, sc, st, sh, bustype, amem_handle, hal_conf_parm, status); + ahp = ar9300_new_state(devid, sc, st, sh, eepromdata, status); if (ahp == AH_NULL) { return AH_NULL; } - ah = &ahp->ah_priv.priv.h; + ah = &ahp->ah_priv.h; ar9300_init_offsets(ah, devid); ahpriv = AH_PRIVATE(ah); - AH_PRIVATE(ah)->ah_bustype = bustype; +// AH_PRIVATE(ah)->ah_bustype = bustype; + + /* FreeBSD: to make OTP work for now, provide this.. */ + AH9300(ah)->ah_cal_mem = ath_hal_malloc(HOST_CALDATA_SIZE); + + /* XXX FreeBSD: enable RX mitigation */ + ah->ah_config.ath_hal_intr_mitigation_rx = 1; + /* + * XXX what's this do? Check in the qcamain driver code + * as to what it does. + */ + ah->ah_config.ath_hal_ext_atten_margin_cfg = 0; /* interrupt mitigation */ #ifdef AR5416_INT_MITIGATION - if (ahpriv->ah_config.ath_hal_intr_mitigation_rx != 0) { + if (ah->ah_config.ath_hal_intr_mitigation_rx != 0) { ahp->ah_intr_mitigation_rx = AH_TRUE; } #else /* Enable Rx mitigation (default) */ ahp->ah_intr_mitigation_rx = AH_TRUE; - ahpriv->ah_config.ath_hal_intr_mitigation_rx = 1; + ah->ah_config.ath_hal_intr_mitigation_rx = 1; #endif #ifdef HOST_OFFLOAD @@ -645,12 +665,12 @@ ar9300_attach(u_int16_t devid, HAL_ADAPT if (AR_SREV_HORNET(ah)) { ahp->ah_intr_mitigation_rx = AH_FALSE; #ifdef AR5416_INT_MITIGATION - ahpriv->ah_config.ath_hal_intr_mitigation_rx = 0; + ah->ah_config.ath_hal_intr_mitigation_rx = 0; #endif } #endif - if (ahpriv->ah_config.ath_hal_intr_mitigation_tx != 0) { + if (ah->ah_config.ath_hal_intr_mitigation_tx != 0) { ahp->ah_intr_mitigation_tx = AH_TRUE; } @@ -685,9 +705,11 @@ ar9300_attach(u_int16_t devid, HAL_ADAPT #if ATH_SUPPORT_MCI if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { +#if 0 ah->ah_bt_coex_set_weights = ar9300_mci_bt_coex_set_weights; ah->ah_bt_coex_disable = ar9300_mci_bt_coex_disable; ah->ah_bt_coex_enable = ar9300_mci_bt_coex_enable; +#endif ahp->ah_mci_ready = AH_FALSE; ahp->ah_mci_bt_state = MCI_BT_SLEEP; ahp->ah_mci_coex_major_version_wlan = MCI_GPM_COEX_MAJOR_VERSION_WLAN; @@ -772,9 +794,9 @@ ar9300_attach(u_int16_t devid, HAL_ADAPT } /* No serialization of Register Accesses needed. */ - ahpriv->ah_config.ath_hal_serialize_reg_mode = SER_REG_MODE_OFF; - HALDEBUG(ah, HAL_DEBUG_RESET, "%s: ath_hal_serialize_reg_mode is %d\n", - __func__, ahpriv->ah_config.ath_hal_serialize_reg_mode); + ah->ah_config.ah_serialise_reg_war = SER_REG_MODE_OFF; + HALDEBUG(ah, HAL_DEBUG_RESET, "%s: ah_serialise_reg_war is %d\n", + __func__, ah->ah_config.ah_serialise_reg_war); /* * Add mac revision check when needed. @@ -798,7 +820,7 @@ ar9300_attach(u_int16_t devid, HAL_ADAPT goto bad; } - ahpriv->ah_phy_rev = OS_REG_READ(ah, AR_PHY_CHIP_ID); + AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); /* Setup supported calibrations */ ahp->ah_iq_cal_data.cal_data = &iq_cal_single_sample; @@ -858,7 +880,7 @@ ar9300_attach(u_int16_t devid, HAL_ADAPT ar9331_modes_lowest_ob_db_tx_gain_hornet1_2, ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5); - ahpriv->ah_config.ath_hal_pcie_power_save_enable = 0; + ah->ah_config.ath_hal_pcie_power_save_enable = 0; /* Japan 2484Mhz CCK settings */ INIT_INI_ARRAY(&ahp->ah_ini_japan2484, @@ -926,7 +948,7 @@ ar9300_attach(u_int16_t devid, HAL_ADAPT ar9331_modes_lowest_ob_db_tx_gain_hornet1_1, ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5); - ahpriv->ah_config.ath_hal_pcie_power_save_enable = 0; + ah->ah_config.ath_hal_pcie_power_save_enable = 0; /* Japan 2484Mhz CCK settings */ INIT_INI_ARRAY(&ahp->ah_ini_japan2484, @@ -1003,13 +1025,13 @@ ar9300_attach(u_int16_t devid, HAL_ADAPT ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484), 2); /* Load PCIE SERDES settings from INI */ - if (ahpriv->ah_config.ath_hal_pcie_clock_req) { + if (ah->ah_config.ath_hal_pcie_clock_req) { /* Pci-e Clock Request = 1 */ - if (ahpriv->ah_config.ath_hal_pll_pwr_save + if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_CONTROL) { /* Sleep Setting */ - if (ahpriv->ah_config.ath_hal_pll_pwr_save & + if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D3) { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, @@ -1025,7 +1047,7 @@ ar9300_attach(u_int16_t devid, HAL_ADAPT 2); } /* Awake Setting */ - if (ahpriv->ah_config.ath_hal_pll_pwr_save & + if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D0) { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, @@ -1056,11 +1078,11 @@ ar9300_attach(u_int16_t devid, HAL_ADAPT } } else { /* Pci-e Clock Request = 0 */ - if (ahpriv->ah_config.ath_hal_pll_pwr_save + if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_CONTROL) { /* Sleep Setting */ - if (ahpriv->ah_config.ath_hal_pll_pwr_save & + if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D3) { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, @@ -1076,7 +1098,7 @@ ar9300_attach(u_int16_t devid, HAL_ADAPT 2); } /* Awake Setting */ - if (ahpriv->ah_config.ath_hal_pll_pwr_save & + if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D0) { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, @@ -1107,7 +1129,7 @@ ar9300_attach(u_int16_t devid, HAL_ADAPT } } /* pcie ps setting will honor registry setting, default is 0 */ - //ahpriv->ah_config.ath_hal_pciePowerSaveEnable = 0; + //ah->ah_config.ath_hal_pciePowerSaveEnable = 0; } else if (AR_SREV_POSEIDON(ah)) { /* mac */ INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); @@ -1160,13 +1182,13 @@ ar9300_attach(u_int16_t devid, HAL_ADAPT ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484), 2); /* Load PCIE SERDES settings from INI */ - if (ahpriv->ah_config.ath_hal_pcie_clock_req) { + if (ah->ah_config.ath_hal_pcie_clock_req) { /* Pci-e Clock Request = 1 */ - if (ahpriv->ah_config.ath_hal_pll_pwr_save + if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_CONTROL) { /* Sleep Setting */ - if (ahpriv->ah_config.ath_hal_pll_pwr_save & + if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D3) { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, @@ -1182,7 +1204,7 @@ ar9300_attach(u_int16_t devid, HAL_ADAPT 2); } /* Awake Setting */ - if (ahpriv->ah_config.ath_hal_pll_pwr_save & + if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D0) { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, @@ -1215,11 +1237,11 @@ ar9300_attach(u_int16_t devid, HAL_ADAPT } } else { /* Pci-e Clock Request = 0 */ - if (ahpriv->ah_config.ath_hal_pll_pwr_save + if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_CONTROL) { /* Sleep Setting */ - if (ahpriv->ah_config.ath_hal_pll_pwr_save & + if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D3) { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, @@ -1235,7 +1257,7 @@ ar9300_attach(u_int16_t devid, HAL_ADAPT 2); } /* Awake Setting */ - if (ahpriv->ah_config.ath_hal_pll_pwr_save & + if (ah->ah_config.ath_hal_pll_pwr_save & AR_PCIE_PLL_PWRSAVE_ON_D0) { INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, @@ -1268,7 +1290,7 @@ ar9300_attach(u_int16_t devid, HAL_ADAPT } } /* pcie ps setting will honor registry setting, default is 0 */ - /*ahpriv->ah_config.ath_hal_pcie_power_save_enable = 0;*/ + /*ah->ah_config.ath_hal_pcie_power_save_enable = 0;*/ #if 0 /* ATH_WOW */ /* SerDes values during WOW sleep */ *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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