Date: Sun, 1 Jun 2014 14:19:13 +0000 (UTC) From: Olli Hauer <ohauer@FreeBSD.org> To: ports-committers@freebsd.org, svn-ports-all@freebsd.org, svn-ports-head@freebsd.org Subject: svn commit: r356126 - head/cad/p5-Verilog-Perl Message-ID: <201406011419.s51EJDpD090845@svn.freebsd.org>
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Author: ohauer Date: Sun Jun 1 14:19:13 2014 New Revision: 356126 URL: http://svnweb.freebsd.org/changeset/ports/356126 QAT: https://qat.redports.org/buildarchive/r356126/ Log: - add stage support - unbreak Modified: head/cad/p5-Verilog-Perl/Makefile head/cad/p5-Verilog-Perl/pkg-plist Modified: head/cad/p5-Verilog-Perl/Makefile ============================================================================== --- head/cad/p5-Verilog-Perl/Makefile Sun Jun 1 14:18:40 2014 (r356125) +++ head/cad/p5-Verilog-Perl/Makefile Sun Jun 1 14:19:13 2014 (r356126) @@ -12,22 +12,9 @@ COMMENT= Building point for Verilog supp BUILD_DEPENDS= flex>=2.5.35:${PORTSDIR}/textproc/flex -BROKEN= not staged USES= bison gmake perl5 USE_PERL5= configure -MAN1= vhier.1 vpassert.1 vppreproc.1 vrename.1 - -MAN3= Verilog::EditFiles.3 Verilog::Netlist::Logger.3 \ - Verilog::Parser.3 Verilog::Getopt.3 Verilog::Netlist::Module.3 \ - Verilog::Preproc.3 Verilog::Language.3 Verilog::Netlist::Net.3 \ - Verilog::SigParser.3 Verilog::Netlist.3 Verilog::Netlist::Pin.3 \ - Verilog::Netlist::Cell.3 Verilog::Netlist::Port.3 Verilog::Netlist::Defparam.3 \ - Verilog::Netlist::File.3 Verilog::Netlist::Subclass.3 \ - Verilog::Netlist::ContAssign.3 Verilog::Netlist::ModPort.3 \ - Verilog::Verilog-Perl.3 Verilog::Netlist::Interface.3 Verilog::Std.3 - -NO_STAGE= yes .include <bsd.port.pre.mk> post-patch: @@ -35,15 +22,10 @@ post-patch: ${WRKSRC}/Makefile.PL @${REINPLACE_CMD} -e 's|make|gmake|g' ${WRKSRC}/Makefile.PL -post-configure: -.if ${OSVERSION} < 700042 - @${REINPLACE_CMD} -e 's|-O2|-O|g' ${WRKSRC}/Makefile -.endif - -post-build: - cd ${WRKSRC} && make test +post-install: + ${STRIP_CMD} ${STAGEDIR}${SITE_PERL}/${PERL_ARCH}/auto/Verilog/Parser/*.so -test: - make post-build +regression-test: build + make test -C ${WRKSRC} .include <bsd.port.post.mk> Modified: head/cad/p5-Verilog-Perl/pkg-plist ============================================================================== --- head/cad/p5-Verilog-Perl/pkg-plist Sun Jun 1 14:18:40 2014 (r356125) +++ head/cad/p5-Verilog-Perl/pkg-plist Sun Jun 1 14:19:13 2014 (r356126) @@ -2,6 +2,27 @@ bin/vhier bin/vpassert bin/vppreproc bin/vrename +%%PERL5_MAN3%%/Verilog::EditFiles.3.gz +%%PERL5_MAN3%%/Verilog::Getopt.3.gz +%%PERL5_MAN3%%/Verilog::Language.3.gz +%%PERL5_MAN3%%/Verilog::Netlist.3.gz +%%PERL5_MAN3%%/Verilog::Netlist::Cell.3.gz +%%PERL5_MAN3%%/Verilog::Netlist::ContAssign.3.gz +%%PERL5_MAN3%%/Verilog::Netlist::Defparam.3.gz +%%PERL5_MAN3%%/Verilog::Netlist::File.3.gz +%%PERL5_MAN3%%/Verilog::Netlist::Interface.3.gz +%%PERL5_MAN3%%/Verilog::Netlist::Logger.3.gz +%%PERL5_MAN3%%/Verilog::Netlist::ModPort.3.gz +%%PERL5_MAN3%%/Verilog::Netlist::Module.3.gz +%%PERL5_MAN3%%/Verilog::Netlist::Net.3.gz +%%PERL5_MAN3%%/Verilog::Netlist::Pin.3.gz +%%PERL5_MAN3%%/Verilog::Netlist::Port.3.gz +%%PERL5_MAN3%%/Verilog::Netlist::Subclass.3.gz +%%PERL5_MAN3%%/Verilog::Parser.3.gz +%%PERL5_MAN3%%/Verilog::Preproc.3.gz +%%PERL5_MAN3%%/Verilog::SigParser.3.gz +%%PERL5_MAN3%%/Verilog::Std.3.gz +%%PERL5_MAN3%%/Verilog::Verilog-Perl.3.gz %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/EditFiles.pm %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Getopt.pm %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Language.pm @@ -28,9 +49,13 @@ bin/vrename %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Parser/Parser.so %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Preproc/Preproc.bs %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Preproc/Preproc.so -@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Preproc -@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Parser -@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Language -@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog +man/man1/vhier.1.gz +man/man1/vpassert.1.gz +man/man1/vppreproc.1.gz +man/man1/vrename.1.gz @dirrm %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist @dirrm %%SITE_PERL%%/%%PERL_ARCH%%/Verilog +@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Language +@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Parser +@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Preproc +@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog
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