Date: Sun, 10 Mar 1996 10:56:24 -0800 (PST) From: Jake Hamby <jehamby@lightside.com> To: "Rodney W. Grimes" <rgrimes@GndRsh.aac.dev.com> Cc: current@FreeBSD.ORG, jkh@time.cdrom.com, toor@dyson.iquest.net Subject: Re: AMD doesn't like SNAP! (panic: unwire: page not in pmap) Message-ID: <Pine.AUX.3.91.960310105357.20948A-100000@covina.lightside.com> In-Reply-To: <199603100445.UAA10659@GndRsh.aac.dev.com>
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On Sat, 9 Mar 1996, Rodney W. Grimes wrote: > > Can all three of you tell me if you have A80486DX4-100NV8T's or > A80486DX4-100SV8B's? The difference is the SV8B is the write back > enhanced DX4 and unless you have a motherboard that understands > how to deal with this you are going to have a cache coherency problem > between the internal and external cache. > > I have yet to see a MB deal with this correctly when faced with > a bus master SCSI controller, though I have seen some that work fine > as long as no bus mastering is occuring. Far more don't work than > do work. > > If you don't have SV8B's or are not running them in WB mode, then > I don't have any idea what has gone wrong... FYI, I have the 100NV8T, so I guess that's not the problem. Whew! Note that the problem occurs with caches enabled OR disabled, I do have a bus mastering SCSI controller (Adaptec 2842VLB), and someone has reported that the problem occurs with the Intel DX2/66, so I guess AMD isn't the common link after all. For future reference, are you saying that the SV8B AMD chips are to be avoided, at least if busmastering SCSI controllers are involved? ---Jake
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