Date: Sat, 5 Jun 2010 16:25:25 +0000 (UTC) From: Nathan Whitehorn <nwhitehorn@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r208836 - head/sys/dev/ata/chipsets Message-ID: <201006051625.o55GPPvR074692@svn.freebsd.org>
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Author: nwhitehorn Date: Sat Jun 5 16:25:25 2010 New Revision: 208836 URL: http://svn.freebsd.org/changeset/base/208836 Log: Partially revert r208162 while waiting for review on a more comprehensive fix. On Apple OpenPICs, the low/high bit of the interrupt sense is only respected for interrupt 0. We currently erroneously program all OpenPIC interrupts level high instead of level low by default, which only matters for some G5 systems where the SATA controllers use IRQ 0. This change is a quick fix that will be reverted once the effect of changing the default interrupt sense on embedded systems is known. MFC after: 3 days Modified: head/sys/dev/ata/chipsets/ata-serverworks.c Modified: head/sys/dev/ata/chipsets/ata-serverworks.c ============================================================================== --- head/sys/dev/ata/chipsets/ata-serverworks.c Sat Jun 5 16:21:55 2010 (r208835) +++ head/sys/dev/ata/chipsets/ata-serverworks.c Sat Jun 5 16:25:25 2010 (r208836) @@ -41,6 +41,9 @@ __FBSDID("$FreeBSD$"); #include <sys/sema.h> #include <sys/taskqueue.h> #include <vm/uma.h> +#ifdef __powerpc__ +#include <machine/intr_machdep.h> +#endif #include <machine/stdarg.h> #include <machine/resource.h> #include <machine/bus.h> @@ -217,6 +220,10 @@ ata_serverworks_ch_attach(device_t dev) ch->hw.tf_write = ata_serverworks_tf_write; #ifdef __powerpc__ ch->hw.status = ata_serverworks_status; + + /* Make sure that our interrupt is edge triggered */ + powerpc_config_intr(bus_get_resource_start(device_get_parent(dev), + SYS_RES_IRQ, 0), INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW); #endif if (ctlr->chip->chipid == ATA_K2) {
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