Date: Sat, 6 May 1995 22:18:20 -0700 (PDT) From: "Rodney W. Grimes" <rgrimes@gndrsh.aac.dev.com> To: terry@cs.weber.edu (Terry Lambert) Cc: tom@haven.uniserve.com, hackers@FreeBSD.org Subject: Re: PCI question Message-ID: <199505070518.WAA11993@gndrsh.aac.dev.com> In-Reply-To: <9505070449.AA27277@cs.weber.edu> from "Terry Lambert" at May 6, 95 10:49:16 pm
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> > > What are the pros and cons of level vs edge triggered interrupts? > > One can run multiple cards (per the PCI spec and per the Intel OEM > products division SMP box implementation) and the other needs an > interrupt per slot, in violation of the spec and impossible on > some hardware (like the Intel OEM products division SMP box). Interrupts per slot are *not* a violation of the spec, the spec allows either implementation. Intel's OEM product divisions BIOS author has been personal flambasted by me for his current PCI interrupt set up code. The response was the spec allows it that way, I am going to do it that way, and if OS's have problems with it the OS is broken. He did not seem to care that forcing shared interrupt dispatching via device polls was very ineffecient from a performance stand point :-(. I was not impresssed, I won't use Intel OEM products for this reason (Oem products are things like the Intel Preimier I/II, aka Plato motherboard). -- Rod Grimes rgrimes@gndrsh.aac.dev.com Accurate Automation Company Custom computers for FreeBSD
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