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Date:      Wed, 25 Aug 2010 12:10:21 +0000 (UTC)
From:      "Jayachandran C." <jchandra@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r211812 - head/sys/mips/rmi
Message-ID:  <201008251210.o7PCALXt010953@svn.freebsd.org>
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Author: jchandra
Date: Wed Aug 25 12:10:20 2010
New Revision: 211812
URL: http://svn.freebsd.org/changeset/base/211812

Log:
  XLR PIC code update.
  - Fix a bug in xlr_pic_init (use irq in PIC_IRQ_IS_EDGE_TRIGGERED)
  - use new macro PIC_INTR_TO_IRQ() and PIC_IRT_x() in xlr_pic_init

Modified:
  head/sys/mips/rmi/pic.h
  head/sys/mips/rmi/xlr_machdep.c

Modified: head/sys/mips/rmi/pic.h
==============================================================================
--- head/sys/mips/rmi/pic.h	Wed Aug 25 11:49:48 2010	(r211811)
+++ head/sys/mips/rmi/pic.h	Wed Aug 25 12:10:20 2010	(r211812)
@@ -93,7 +93,6 @@
 #define	PIC_TIMER_COUNT_0_BASE		0x120
 #define	PIC_TIMER_COUNT_1_BASE		0x130
 
-
 #define	PIC_IRT_0(picintr)	(PIC_IRT_0_BASE + (picintr))
 #define	PIC_IRT_1(picintr)	(PIC_IRT_1_BASE + (picintr))
 
@@ -102,7 +101,14 @@
 #define	PIC_TIMER_COUNT_0(i)	(PIC_TIMER_COUNT_0_BASE + (i))
 #define	PIC_TIMER_COUNT_1(i)	(PIC_TIMER_COUNT_0_BASE + (i))
 
+/*
+ * We use a simple mapping form PIC interrupts to CPU IRQs.
+ * The PIC interrupts 0-31 are mapped to CPU irq's 8-39.
+ * this leaves the lower 0-7 for the cpu interrupts (like 
+ * count/compare, msgrng) and 40-63 for IPIs
+ */
 #define	PIC_IRQ_BASE		8
+#define	PIC_INTR_TO_IRQ(i)	(PIC_IRQ_BASE + (i))
 #define	PIC_IRT_FIRST_IRQ	PIC_IRQ_BASE
 
 #define	PIC_WD_IRQ		(PIC_IRQ_BASE + PIC_IRT_WD_INDEX)

Modified: head/sys/mips/rmi/xlr_machdep.c
==============================================================================
--- head/sys/mips/rmi/xlr_machdep.c	Wed Aug 25 11:49:48 2010	(r211811)
+++ head/sys/mips/rmi/xlr_machdep.c	Wed Aug 25 12:10:20 2010	(r211812)
@@ -282,22 +282,23 @@ static void 
 xlr_pic_init(void)
 {
 	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
-	int i, level;
+	int i, level, irq;
 
 	mtx_init(&xlr_pic_lock, "pic", NULL, MTX_SPIN);
 	xlr_write_reg(mmio, PIC_CTRL, 0);
 	for (i = 0; i < PIC_NUM_IRTS; i++) {
-		level = PIC_IRQ_IS_EDGE_TRIGGERED(i);
+		irq = PIC_INTR_TO_IRQ(i);
+		level = PIC_IRQ_IS_EDGE_TRIGGERED(irq);
 
 		/* Bind all PIC irqs to cpu 0 */
-		xlr_write_reg(mmio, PIC_IRT_0_BASE + i, 0x01);
+		xlr_write_reg(mmio, PIC_IRT_0(i), 0x01);
 
 		/*
 		 * Use local scheduling and high polarity for all IRTs
 		 * Invalidate all IRTs, by default
 		 */
-		xlr_write_reg(mmio, PIC_IRT_1_BASE + i, (level << 30) | (1 << 6) |
-		    (PIC_IRQ_BASE + i));
+		xlr_write_reg(mmio, PIC_IRT_1(i), (level << 30) | (1 << 6) |
+		    irq);
 	}
 }

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