Date: Tue, 18 Mar 2014 12:19:39 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r263296 - head/sys/mips/atheros Message-ID: <201403181219.s2ICJd6O027918@svn.freebsd.org>
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Author: adrian Date: Tue Mar 18 12:19:39 2014 New Revision: 263296 URL: http://svnweb.freebsd.org/changeset/base/263296 Log: Extend the Atheros SoC support to include a method to enable/disable the NAND flash controller. Add the AR934x NAND flash controller reset routines. (It's different on subsequent SoCs.) Tested: * AR9344, Atheros DB120 reference platform Obtained from: OpenWRT Modified: head/sys/mips/atheros/ar71xx_cpudef.h head/sys/mips/atheros/ar934x_chip.c Modified: head/sys/mips/atheros/ar71xx_cpudef.h ============================================================================== --- head/sys/mips/atheros/ar71xx_cpudef.h Tue Mar 18 12:18:35 2014 (r263295) +++ head/sys/mips/atheros/ar71xx_cpudef.h Tue Mar 18 12:19:39 2014 (r263296) @@ -63,6 +63,8 @@ struct ar71xx_cpu_def { void (* ar71xx_chip_reset_wmac) (void); void (* ar71xx_chip_init_gmac) (void); + + void (* ar71xx_chip_reset_nfc) (int); }; extern struct ar71xx_cpu_def * ar71xx_cpu_ops; @@ -140,6 +142,13 @@ static inline void ar71xx_device_ddr_flu ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ip2(); } +static inline void ar71xx_reset_nfc(int active) +{ + + if (ar71xx_cpu_ops->ar71xx_chip_reset_nfc) + ar71xx_cpu_ops->ar71xx_chip_reset_nfc(active); +} + /* XXX shouldn't be here! */ extern uint32_t u_ar71xx_refclk; extern uint32_t u_ar71xx_cpu_freq; Modified: head/sys/mips/atheros/ar934x_chip.c ============================================================================== --- head/sys/mips/atheros/ar934x_chip.c Tue Mar 18 12:18:35 2014 (r263295) +++ head/sys/mips/atheros/ar934x_chip.c Tue Mar 18 12:19:39 2014 (r263296) @@ -375,6 +375,7 @@ static void ar934x_chip_reset_wmac(void) { + /* XXX TODO */ } static void @@ -391,6 +392,31 @@ ar934x_chip_init_gmac(void) } } +/* + * Reset the NAND Flash Controller. + * + * + active=1 means "make it active". + * + active=0 means "make it inactive". + */ +static void +ar934x_chip_reset_nfc(int active) +{ + + if (active) { + ar71xx_device_start(AR934X_RESET_NANDF); + DELAY(100); + + ar71xx_device_start(AR934X_RESET_ETH_SWITCH_ANALOG); + DELAY(250); + } else { + ar71xx_device_stop(AR934X_RESET_ETH_SWITCH_ANALOG); + DELAY(250); + + ar71xx_device_stop(AR934X_RESET_NANDF); + DELAY(100); + } +} + struct ar71xx_cpu_def ar934x_chip_def = { &ar934x_chip_detect_mem_size, &ar934x_chip_detect_sys_frequency, @@ -407,4 +433,5 @@ struct ar71xx_cpu_def ar934x_chip_def = &ar934x_chip_reset_ethernet_switch, &ar934x_chip_reset_wmac, &ar934x_chip_init_gmac, + &ar934x_chip_reset_nfc, };
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