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Date:      Tue, 3 Nov 2009 01:33:16 GMT
From:      Otacílio de Araújo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
To:        freebsd-gnats-submit@FreeBSD.org
Subject:   ports/140231: [maintainer update] cad/p5-Verilog-Perl Upgrading to use version 3.221
Message-ID:  <200911030133.nA31XG0G059110@www.freebsd.org>
Resent-Message-ID: <200911030140.nA31e224095276@freefall.freebsd.org>

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>Number:         140231
>Category:       ports
>Synopsis:       [maintainer update] cad/p5-Verilog-Perl Upgrading to use version 3.221
>Confidential:   no
>Severity:       non-critical
>Priority:       low
>Responsible:    freebsd-ports-bugs
>State:          open
>Quarter:        
>Keywords:       
>Date-Required:
>Class:          maintainer-update
>Submitter-Id:   current-users
>Arrival-Date:   Tue Nov 03 01:40:02 UTC 2009
>Closed-Date:
>Last-Modified:
>Originator:     Otacílio de Araújo Ramos Neto
>Release:        7.2-RELEASE-p3
>Organization:
>Environment:
squitch# uname -a
FreeBSD squitch 7.2-RELEASE-p3 FreeBSD 7.2-RELEASE-p3 #0: Sun Sep 27 19:34:18 BRT 2009     ota@squitch:/usr/obj/usr/src/sys/SQUITCH  i386

>Description:
Updating of port p5-Verilog-Perl.
>How-To-Repeat:

>Fix:


Patch attached with submission follows:

===> Generating patch
===> Viewing diff with more
diff -ruN --exclude=CVS /usr/ports/cad/p5-Verilog-Perl/Makefile /usr/ports/cad/p5-Verilog-Perl.new/Makefile
--- /usr/ports/cad/p5-Verilog-Perl/Makefile	2009-09-15 10:16:14.000000000 -0300
+++ /usr/ports/cad/p5-Verilog-Perl.new/Makefile	2009-11-02 22:16:47.000000000 -0200
@@ -1,12 +1,12 @@
 # New ports collection makefile for:   Verilog-Perl
 # Date created:                11 Apr 2009
-# Whom:                        Otacílio de Araújo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
+# Whom:                        Otacilio de Araujo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
 #
-# $FreeBSD: ports/cad/p5-Verilog-Perl/Makefile,v 1.6 2009/09/15 13:16:14 az Exp $
+# $FreeBSD: ports/cad/p5-Verilog-Perl/Makefile,v 1.2 2009/05/26 11:54:56 garga Exp $
 #
 
 PORTNAME=	Verilog-Perl
-PORTVERSION=	3.212
+PORTVERSION=	3.221
 CATEGORIES=	cad perl5
 MASTER_SITES=	CPAN
 PKGNAMEPREFIX=	p5-
@@ -30,6 +30,7 @@
 	Verilog::SigParser.3 Verilog::Netlist.3 Verilog::Netlist::Pin.3 \
 	Verilog::Netlist::Cell.3 Verilog::Netlist::Port.3 \
 	Verilog::Netlist::File.3 Verilog::Netlist::Subclass.3 \
+	Verilog::Netlist::ContAssign.3 \
 	Verilog::Verilog-Perl.3 Verilog::Netlist::Interface.3 Verilog::Std.3
 
 .include <bsd.port.pre.mk>
diff -ruN --exclude=CVS /usr/ports/cad/p5-Verilog-Perl/distinfo /usr/ports/cad/p5-Verilog-Perl.new/distinfo
--- /usr/ports/cad/p5-Verilog-Perl/distinfo	2009-08-24 03:01:24.000000000 -0300
+++ /usr/ports/cad/p5-Verilog-Perl.new/distinfo	2009-10-29 11:49:59.000000000 -0200
@@ -1,3 +1,3 @@
-MD5 (Verilog-Perl-3.212.tar.gz) = 5682e42a4904d41206782128b174a7d1
-SHA256 (Verilog-Perl-3.212.tar.gz) = 8d6829d1062bfd7a343df27c1efeb15a2e79abfc17bafb5e3e8acdf989ad3fd0
-SIZE (Verilog-Perl-3.212.tar.gz) = 203811
+MD5 (Verilog-Perl-3.221.tar.gz) = 75f43ca63bcbe927efeabc80830c8dbd
+SHA256 (Verilog-Perl-3.221.tar.gz) = 443b4875416592b4d1c12652b1507fe78f4123f94951fd30fdabea6e674c4e3f
+SIZE (Verilog-Perl-3.221.tar.gz) = 210188
diff -ruN --exclude=CVS /usr/ports/cad/p5-Verilog-Perl/patch /usr/ports/cad/p5-Verilog-Perl.new/patch
--- /usr/ports/cad/p5-Verilog-Perl/patch	1969-12-31 21:00:00.000000000 -0300
+++ /usr/ports/cad/p5-Verilog-Perl.new/patch	2009-11-02 22:32:03.000000000 -0200
@@ -0,0 +1 @@
+===> Generating patch
diff -ruN --exclude=CVS /usr/ports/cad/p5-Verilog-Perl/pkg-plist /usr/ports/cad/p5-Verilog-Perl.new/pkg-plist
--- /usr/ports/cad/p5-Verilog-Perl/pkg-plist	2009-07-14 21:42:29.000000000 -0300
+++ /usr/ports/cad/p5-Verilog-Perl.new/pkg-plist	2009-10-29 11:49:59.000000000 -0200
@@ -15,6 +15,7 @@
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Pin.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Port.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Subclass.pm
+%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ContAssign.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Parser.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Preproc.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/SigParser.pm
===> Done


>Release-Note:
>Audit-Trail:
>Unformatted:



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