Date: Sat, 16 Feb 2008 03:26:49 GMT From: Kip Macy <kmacy@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 135473 for review Message-ID: <200802160326.m1G3QnAp071336@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=135473 Change 135473 by kmacy@kmacy:entropy:iwarp on 2008/02/16 03:26:22 Integrate support for firmware rev 5.0 and with support for the T3C chip Affected files ... .. //depot/projects/iwarp/sys/dev/cxgb/common/cxgb_ael1002.c#2 edit .. //depot/projects/iwarp/sys/dev/cxgb/common/cxgb_common.h#3 edit .. //depot/projects/iwarp/sys/dev/cxgb/common/cxgb_firmware_exports.h#2 edit .. //depot/projects/iwarp/sys/dev/cxgb/common/cxgb_mc5.c#2 edit .. //depot/projects/iwarp/sys/dev/cxgb/common/cxgb_mv88e1xxx.c#2 edit .. //depot/projects/iwarp/sys/dev/cxgb/common/cxgb_regs.h#2 edit .. //depot/projects/iwarp/sys/dev/cxgb/common/cxgb_t3_cpl.h#4 edit .. //depot/projects/iwarp/sys/dev/cxgb/common/cxgb_t3_hw.c#5 edit .. //depot/projects/iwarp/sys/dev/cxgb/common/cxgb_tcb.h#2 edit .. //depot/projects/iwarp/sys/dev/cxgb/common/cxgb_version.h#2 edit .. //depot/projects/iwarp/sys/dev/cxgb/common/cxgb_vsc8211.c#2 edit .. //depot/projects/iwarp/sys/dev/cxgb/common/cxgb_xgmac.c#2 edit .. //depot/projects/iwarp/sys/dev/cxgb/cxgb_adapter.h#13 edit .. //depot/projects/iwarp/sys/dev/cxgb/cxgb_ioctl.h#3 edit .. //depot/projects/iwarp/sys/dev/cxgb/cxgb_main.c#15 edit .. //depot/projects/iwarp/sys/dev/cxgb/cxgb_offload.c#17 edit .. //depot/projects/iwarp/sys/dev/cxgb/cxgb_osdep.h#8 edit .. //depot/projects/iwarp/sys/dev/cxgb/cxgb_sge.c#13 edit .. //depot/projects/iwarp/sys/dev/cxgb/t3cdev.h#5 edit .. //depot/projects/iwarp/sys/dev/cxgb/ulp/toecore/cxgb_toedev.h#3 edit .. //depot/projects/iwarp/sys/dev/cxgb/ulp/tom/cxgb_cpl_io.c#13 edit .. //depot/projects/iwarp/sys/dev/cxgb/ulp/tom/cxgb_cpl_socket.c#11 edit .. //depot/projects/iwarp/sys/dev/cxgb/ulp/tom/cxgb_ddp.c#5 edit .. //depot/projects/iwarp/sys/dev/cxgb/ulp/tom/cxgb_defs.h#9 integrate .. //depot/projects/iwarp/sys/dev/cxgb/ulp/tom/cxgb_listen.c#4 integrate .. //depot/projects/iwarp/sys/dev/cxgb/ulp/tom/cxgb_t3_ddp.h#6 edit .. //depot/projects/iwarp/sys/dev/cxgb/ulp/tom/cxgb_tom.c#8 edit .. //depot/projects/iwarp/sys/modules/cxgb/cxgb/Makefile#7 edit Differences ... ==== //depot/projects/iwarp/sys/dev/cxgb/common/cxgb_ael1002.c#2 (text+ko) ==== @@ -36,6 +36,9 @@ #include <dev/cxgb/cxgb_include.h> #endif +#undef msleep +#define msleep t3_os_sleep + enum { AEL100X_TX_DISABLE = 9, AEL100X_TX_CONFIG1 = 0xc002, @@ -52,9 +55,9 @@ { int tx_on_gpio = phy->addr == 0 ? F_GPIO7_OUT_VAL : F_GPIO2_OUT_VAL; - t3_os_sleep(100); + msleep(100); t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio); - t3_os_sleep(30); + msleep(30); } static int ael1002_power_down(struct cphy *phy, int enable) @@ -115,7 +118,6 @@ #ifdef C99_NOT_SUPPORTED static struct cphy_ops ael1002_ops = { - NULL, ael1002_reset, ael1002_intr_noop, ael1002_intr_noop, @@ -141,11 +143,14 @@ }; #endif -void t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, - const struct mdio_ops *mdio_ops) +int t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, + const struct mdio_ops *mdio_ops) { - cphy_init(phy, adapter, phy_addr, &ael1002_ops, mdio_ops); + cphy_init(phy, adapter, phy_addr, &ael1002_ops, mdio_ops, + SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE, + "10GBASE-XR"); ael100x_txon(phy); + return 0; } static int ael1006_reset(struct cphy *phy, int wait) @@ -188,7 +193,6 @@ #ifdef C99_NOT_SUPPORTED static struct cphy_ops ael1006_ops = { - NULL, ael1006_reset, ael1006_intr_enable, ael1006_intr_disable, @@ -214,16 +218,18 @@ }; #endif -void t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, - const struct mdio_ops *mdio_ops) +int t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, + const struct mdio_ops *mdio_ops) { - cphy_init(phy, adapter, phy_addr, &ael1006_ops, mdio_ops); + cphy_init(phy, adapter, phy_addr, &ael1006_ops, mdio_ops, + SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE, + "10GBASE-SR"); ael100x_txon(phy); + return 0; } #ifdef C99_NOT_SUPPORTED static struct cphy_ops qt2045_ops = { - NULL, ael1006_reset, ael1006_intr_enable, ael1006_intr_disable, @@ -249,12 +255,14 @@ }; #endif -void t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, - const struct mdio_ops *mdio_ops) +int t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, + const struct mdio_ops *mdio_ops) { unsigned int stat; - cphy_init(phy, adapter, phy_addr, &qt2045_ops, mdio_ops); + cphy_init(phy, adapter, phy_addr, &qt2045_ops, mdio_ops, + SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_TP, + "10GBASE-CX4"); /* * Some cards where the PHY is supposed to be at address 0 actually @@ -263,6 +271,7 @@ if (!phy_addr && !mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMSR, &stat) && stat == 0xffff) phy->addr = 1; + return 0; } static int xaui_direct_reset(struct cphy *phy, int wait) @@ -300,7 +309,6 @@ #ifdef C99_NOT_SUPPORTED static struct cphy_ops xaui_direct_ops = { - NULL, xaui_direct_reset, ael1002_intr_noop, ael1002_intr_noop, @@ -326,8 +334,11 @@ }; #endif -void t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, - const struct mdio_ops *mdio_ops) +int t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, + const struct mdio_ops *mdio_ops) { - cphy_init(phy, adapter, phy_addr, &xaui_direct_ops, mdio_ops); + cphy_init(phy, adapter, phy_addr, &xaui_direct_ops, mdio_ops, + SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_TP, + "10GBASE-CX4"); + return 0; } ==== //depot/projects/iwarp/sys/dev/cxgb/common/cxgb_common.h#3 (text+ko) ==== @@ -98,9 +98,9 @@ (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO) enum { - FW_VERSION_MAJOR = 4, - FW_VERSION_MINOR = 7, - FW_VERSION_MICRO = 1 + FW_VERSION_MAJOR = 5, + FW_VERSION_MINOR = 0, + FW_VERSION_MICRO = 0 }; enum { @@ -157,10 +157,10 @@ }; struct port_type_info { - void (*phy_prep)(struct cphy *phy, adapter_t *adapter, int phy_addr, - const struct mdio_ops *ops); - unsigned int caps; - const char *desc; + int (*phy_prep)(struct cphy *phy, adapter_t *adapter, int phy_addr, + const struct mdio_ops *ops); + + }; struct mc5_stats { @@ -508,7 +508,6 @@ /* PHY operations */ struct cphy_ops { - void (*destroy)(struct cphy *phy); int (*reset)(struct cphy *phy, int wait); int (*intr_enable)(struct cphy *phy); @@ -530,7 +529,9 @@ /* A PHY instance */ struct cphy { int addr; /* PHY address */ + unsigned int caps; /* PHY capabilities */ adapter_t *adapter; /* associated adapter */ + const char *desc; /* PHY description */ unsigned long fifo_errors; /* FIFO over/under-flows */ const struct cphy_ops *ops; /* PHY operations */ int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr, @@ -555,10 +556,13 @@ /* Convenience initializer */ static inline void cphy_init(struct cphy *phy, adapter_t *adapter, int phy_addr, struct cphy_ops *phy_ops, - const struct mdio_ops *mdio_ops) + const struct mdio_ops *mdio_ops, unsigned int caps, + const char *desc) { phy->adapter = adapter; phy->addr = phy_addr; + phy->caps = caps; + phy->desc = desc; phy->ops = phy_ops; if (mdio_ops) { phy->mdio_read = mdio_ops->read; @@ -667,11 +671,12 @@ int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords, u32 *data, int byte_oriented); int t3_get_tp_version(adapter_t *adapter, u32 *vers); -int t3_check_tpsram_version(adapter_t *adapter); +int t3_check_tpsram_version(adapter_t *adapter, int *must_load); int t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size); int t3_load_fw(adapter_t *adapter, const const u8 *fw_data, unsigned int size); +int t3_load_boot(adapter_t *adapter, u8 *boot_data, unsigned int size); int t3_get_fw_version(adapter_t *adapter, u32 *vers); -int t3_check_fw_version(adapter_t *adapter); +int t3_check_fw_version(adapter_t *adapter, int *must_load); int t3_init_hw(adapter_t *adapter, u32 fw_params); void mac_prep(struct cmac *mac, adapter_t *adapter, int index); void early_hw_init(adapter_t *adapter, const struct adapter_info *ai); @@ -769,18 +774,21 @@ int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port); int t3_vsc7323_enable(adapter_t *adap, int port, int which); int t3_vsc7323_disable(adapter_t *adap, int port, int which); + +int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert); + const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac); -void t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, +int t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, const struct mdio_ops *mdio_ops); -void t3_vsc8211_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, +int t3_vsc8211_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, const struct mdio_ops *mdio_ops); -void t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, +int t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, const struct mdio_ops *mdio_ops); -void t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, +int t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, const struct mdio_ops *mdio_ops); -void t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, +int t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, const struct mdio_ops *mdio_ops); -void t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, +int t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, const struct mdio_ops *mdio_ops); #endif /* __CHELSIO_COMMON_H */ ==== //depot/projects/iwarp/sys/dev/cxgb/common/cxgb_firmware_exports.h#2 (text+ko) ==== @@ -74,6 +74,8 @@ #define FW_WROPCODE_MNGT 0x1D #define FW_MNGTOPCODE_PKTSCHED_SET 0x00 +#define FW_MNGTOPCODE_WRC_SET 0x01 +#define FW_MNGTOPCODE_TUNNEL_CR_FLUSH 0x02 /* Maximum size of a WR sent from the host, limited by the SGE. * ==== //depot/projects/iwarp/sys/dev/cxgb/common/cxgb_mc5.c#2 (text+ko) ==== @@ -384,7 +384,7 @@ return err; } -/* +/** * read_mc5_range - dump a part of the memory managed by MC5 * @mc5: the MC5 handle * @start: the start address for the dump @@ -425,8 +425,11 @@ #define MC5_INT_FATAL (F_PARITYERR | F_REQQPARERR | F_DISPQPARERR) -/* - * MC5 interrupt handler +/** + * t3_mc5_intr_handler - MC5 interrupt handler + * @mc5: the MC5 handle + * + * The MC5 interrupt handler. */ void t3_mc5_intr_handler(struct mc5 *mc5) { @@ -462,6 +465,16 @@ t3_write_reg(adap, A_MC5_DB_INT_CAUSE, cause); } + +/** + * t3_mc5_prep - initialize the SW state for MC5 + * @adapter: the adapter + * @mc5: the MC5 handle + * @mode: whether the TCAM will be in 72- or 144-bit mode + * + * Initialize the SW state associated with MC5. Among other things + * this determines the size of the attached TCAM. + */ void __devinit t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode) { #define K * 1024 ==== //depot/projects/iwarp/sys/dev/cxgb/common/cxgb_mv88e1xxx.c#2 (text+ko) ==== @@ -221,6 +221,16 @@ return 0; } +static int mv88e1xxx_set_speed_duplex(struct cphy *phy, int speed, int duplex) +{ + int err = t3_set_phy_speed_duplex(phy, speed, duplex); + + /* PHY needs reset for new settings to take effect */ + if (!err) + err = mv88e1xxx_reset(phy, 0); + return err; +} + static int mv88e1xxx_downshift_set(struct cphy *cphy, int downshift_enable) { /* @@ -258,7 +268,6 @@ #ifdef C99_NOT_SUPPORTED static struct cphy_ops mv88e1xxx_ops = { - NULL, mv88e1xxx_reset, mv88e1xxx_intr_enable, mv88e1xxx_intr_disable, @@ -268,7 +277,7 @@ mv88e1xxx_autoneg_restart, t3_phy_advertise, mv88e1xxx_set_loopback, - t3_set_phy_speed_duplex, + mv88e1xxx_set_speed_duplex, mv88e1xxx_get_link_status, mv88e1xxx_power_down, }; @@ -283,20 +292,28 @@ .autoneg_restart = mv88e1xxx_autoneg_restart, .advertise = t3_phy_advertise, .set_loopback = mv88e1xxx_set_loopback, - .set_speed_duplex = t3_set_phy_speed_duplex, + .set_speed_duplex = mv88e1xxx_set_speed_duplex, .get_link_status = mv88e1xxx_get_link_status, .power_down = mv88e1xxx_power_down, }; #endif -void t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, +int t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, const struct mdio_ops *mdio_ops) { - cphy_init(phy, adapter, phy_addr, &mv88e1xxx_ops, mdio_ops); + int err; + + cphy_init(phy, adapter, phy_addr, &mv88e1xxx_ops, mdio_ops, + SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full | + SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_MII | + SUPPORTED_TP | SUPPORTED_IRQ, "10/100/1000BASE-T"); /* Configure copper PHY transmitter as class A to reduce EMI. */ - mdio_write(phy, 0, MV88E1XXX_EXTENDED_ADDR, 0xb); - mdio_write(phy, 0, MV88E1XXX_EXTENDED_DATA, 0x8004); - - mv88e1xxx_downshift_set(phy, 1); /* Enable downshift */ + err = mdio_write(phy, 0, MV88E1XXX_EXTENDED_ADDR, 0xb); + + if (!err) + err = mdio_write(phy, 0, MV88E1XXX_EXTENDED_DATA, 0x8004); + if (!err) + err = mv88e1xxx_downshift_set(phy, 1); /* Enable downshift */ + return err; } ==== //depot/projects/iwarp/sys/dev/cxgb/common/cxgb_regs.h#2 (text+ko) ==== @@ -35,6 +35,38 @@ #define A_SG_CONTROL 0x0 +#define S_CONGMODE 29 +#define V_CONGMODE(x) ((x) << S_CONGMODE) +#define F_CONGMODE V_CONGMODE(1U) + +#define S_TNLFLMODE 28 +#define V_TNLFLMODE(x) ((x) << S_TNLFLMODE) +#define F_TNLFLMODE V_TNLFLMODE(1U) + +#define S_FATLPERREN 27 +#define V_FATLPERREN(x) ((x) << S_FATLPERREN) +#define F_FATLPERREN V_FATLPERREN(1U) + +#define S_URGTNL 26 +#define V_URGTNL(x) ((x) << S_URGTNL) +#define F_URGTNL V_URGTNL(1U) + +#define S_NEWNOTIFY 25 +#define V_NEWNOTIFY(x) ((x) << S_NEWNOTIFY) +#define F_NEWNOTIFY V_NEWNOTIFY(1U) + +#define S_AVOIDCQOVFL 24 +#define V_AVOIDCQOVFL(x) ((x) << S_AVOIDCQOVFL) +#define F_AVOIDCQOVFL V_AVOIDCQOVFL(1U) + +#define S_OPTONEINTMULTQ 23 +#define V_OPTONEINTMULTQ(x) ((x) << S_OPTONEINTMULTQ) +#define F_OPTONEINTMULTQ V_OPTONEINTMULTQ(1U) + +#define S_CQCRDTCTRL 22 +#define V_CQCRDTCTRL(x) ((x) << S_CQCRDTCTRL) +#define F_CQCRDTCTRL V_CQCRDTCTRL(1U) + #define S_EGRENUPBP 21 #define V_EGRENUPBP(x) ((x) << S_EGRENUPBP) #define F_EGRENUPBP V_EGRENUPBP(1U) @@ -94,26 +126,6 @@ #define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE) #define F_GLOBALENABLE V_GLOBALENABLE(1U) -#define S_URGTNL 26 -#define V_URGTNL(x) ((x) << S_URGTNL) -#define F_URGTNL V_URGTNL(1U) - -#define S_NEWNOTIFY 25 -#define V_NEWNOTIFY(x) ((x) << S_NEWNOTIFY) -#define F_NEWNOTIFY V_NEWNOTIFY(1U) - -#define S_AVOIDCQOVFL 24 -#define V_AVOIDCQOVFL(x) ((x) << S_AVOIDCQOVFL) -#define F_AVOIDCQOVFL V_AVOIDCQOVFL(1U) - -#define S_OPTONEINTMULTQ 23 -#define V_OPTONEINTMULTQ(x) ((x) << S_OPTONEINTMULTQ) -#define F_OPTONEINTMULTQ V_OPTONEINTMULTQ(1U) - -#define S_CQCRDTCTRL 22 -#define V_CQCRDTCTRL(x) ((x) << S_CQCRDTCTRL) -#define F_CQCRDTCTRL V_CQCRDTCTRL(1U) - #define A_SG_KDOORBELL 0x4 #define S_SELEGRCNTX 31 @@ -366,11 +378,6 @@ #define A_SG_EGR_PRI_CNT 0x50 -#define S_EGRPRICNT 0 -#define M_EGRPRICNT 0x1f -#define V_EGRPRICNT(x) ((x) << S_EGRPRICNT) -#define G_EGRPRICNT(x) (((x) >> S_EGRPRICNT) & M_EGRPRICNT) - #define S_EGRERROPCODE 24 #define M_EGRERROPCODE 0xff #define V_EGRERROPCODE(x) ((x) << S_EGRERROPCODE) @@ -386,6 +393,11 @@ #define V_EGRLOOPCODE(x) ((x) << S_EGRLOOPCODE) #define G_EGRLOOPCODE(x) (((x) >> S_EGRLOOPCODE) & M_EGRLOOPCODE) +#define S_EGRPRICNT 0 +#define M_EGRPRICNT 0x1f +#define V_EGRPRICNT(x) ((x) << S_EGRPRICNT) +#define G_EGRPRICNT(x) (((x) >> S_EGRPRICNT) & M_EGRPRICNT) + #define A_SG_EGR_RCQ_DRB_THRSH 0x54 #define S_HIRCQDRBTHRSH 16 @@ -407,6 +419,56 @@ #define A_SG_INT_CAUSE 0x5c +#define S_HIRCQPARITYERROR 31 +#define V_HIRCQPARITYERROR(x) ((x) << S_HIRCQPARITYERROR) +#define F_HIRCQPARITYERROR V_HIRCQPARITYERROR(1U) + +#define S_LORCQPARITYERROR 30 +#define V_LORCQPARITYERROR(x) ((x) << S_LORCQPARITYERROR) +#define F_LORCQPARITYERROR V_LORCQPARITYERROR(1U) + +#define S_HIDRBPARITYERROR 29 +#define V_HIDRBPARITYERROR(x) ((x) << S_HIDRBPARITYERROR) +#define F_HIDRBPARITYERROR V_HIDRBPARITYERROR(1U) + +#define S_LODRBPARITYERROR 28 +#define V_LODRBPARITYERROR(x) ((x) << S_LODRBPARITYERROR) +#define F_LODRBPARITYERROR V_LODRBPARITYERROR(1U) + +#define S_FLPARITYERROR 22 +#define M_FLPARITYERROR 0x3f +#define V_FLPARITYERROR(x) ((x) << S_FLPARITYERROR) +#define G_FLPARITYERROR(x) (((x) >> S_FLPARITYERROR) & M_FLPARITYERROR) + +#define S_ITPARITYERROR 20 +#define M_ITPARITYERROR 0x3 +#define V_ITPARITYERROR(x) ((x) << S_ITPARITYERROR) +#define G_ITPARITYERROR(x) (((x) >> S_ITPARITYERROR) & M_ITPARITYERROR) + +#define S_IRPARITYERROR 19 +#define V_IRPARITYERROR(x) ((x) << S_IRPARITYERROR) +#define F_IRPARITYERROR V_IRPARITYERROR(1U) + +#define S_RCPARITYERROR 18 +#define V_RCPARITYERROR(x) ((x) << S_RCPARITYERROR) +#define F_RCPARITYERROR V_RCPARITYERROR(1U) + +#define S_OCPARITYERROR 17 +#define V_OCPARITYERROR(x) ((x) << S_OCPARITYERROR) +#define F_OCPARITYERROR V_OCPARITYERROR(1U) + +#define S_CPPARITYERROR 16 +#define V_CPPARITYERROR(x) ((x) << S_CPPARITYERROR) +#define F_CPPARITYERROR V_CPPARITYERROR(1U) + +#define S_R_REQ_FRAMINGERROR 15 +#define V_R_REQ_FRAMINGERROR(x) ((x) << S_R_REQ_FRAMINGERROR) +#define F_R_REQ_FRAMINGERROR V_R_REQ_FRAMINGERROR(1U) + +#define S_UC_REQ_FRAMINGERROR 14 +#define V_UC_REQ_FRAMINGERROR(x) ((x) << S_UC_REQ_FRAMINGERROR) +#define F_UC_REQ_FRAMINGERROR V_UC_REQ_FRAMINGERROR(1U) + #define S_HICTLDRBDROPERR 13 #define V_HICTLDRBDROPERR(x) ((x) << S_HICTLDRBDROPERR) #define F_HICTLDRBDROPERR V_HICTLDRBDROPERR(1U) @@ -582,6 +644,10 @@ #define A_PCIX_INT_CAUSE 0x84 #define A_PCIX_CFG 0x88 +#define S_DMASTOPEN 19 +#define V_DMASTOPEN(x) ((x) << S_DMASTOPEN) +#define F_DMASTOPEN V_DMASTOPEN(1U) + #define S_CLIDECEN 18 #define V_CLIDECEN(x) ((x) << S_CLIDECEN) #define F_CLIDECEN V_CLIDECEN(1U) @@ -721,16 +787,175 @@ #define V_SLEEPMODE0(x) ((x) << S_SLEEPMODE0) #define F_SLEEPMODE0 V_SLEEPMODE0(1U) +#define A_PCIX_STAT0 0x98 + +#define S_PIOREQFIFOLEVEL 26 +#define M_PIOREQFIFOLEVEL 0x3f +#define V_PIOREQFIFOLEVEL(x) ((x) << S_PIOREQFIFOLEVEL) +#define G_PIOREQFIFOLEVEL(x) (((x) >> S_PIOREQFIFOLEVEL) & M_PIOREQFIFOLEVEL) + +#define S_RFINIST 24 +#define M_RFINIST 0x3 +#define V_RFINIST(x) ((x) << S_RFINIST) +#define G_RFINIST(x) (((x) >> S_RFINIST) & M_RFINIST) + +#define S_RFRESPRDST 22 +#define M_RFRESPRDST 0x3 +#define V_RFRESPRDST(x) ((x) << S_RFRESPRDST) +#define G_RFRESPRDST(x) (((x) >> S_RFRESPRDST) & M_RFRESPRDST) + +#define S_TARCST 19 +#define M_TARCST 0x7 +#define V_TARCST(x) ((x) << S_TARCST) +#define G_TARCST(x) (((x) >> S_TARCST) & M_TARCST) + +#define S_TARXST 16 +#define M_TARXST 0x7 +#define V_TARXST(x) ((x) << S_TARXST) +#define G_TARXST(x) (((x) >> S_TARXST) & M_TARXST) + +#define S_WFREQWRST 13 +#define M_WFREQWRST 0x7 +#define V_WFREQWRST(x) ((x) << S_WFREQWRST) +#define G_WFREQWRST(x) (((x) >> S_WFREQWRST) & M_WFREQWRST) + +#define S_WFRESPFIFOEMPTY 12 +#define V_WFRESPFIFOEMPTY(x) ((x) << S_WFRESPFIFOEMPTY) +#define F_WFRESPFIFOEMPTY V_WFRESPFIFOEMPTY(1U) + +#define S_WFREQFIFOEMPTY 11 +#define V_WFREQFIFOEMPTY(x) ((x) << S_WFREQFIFOEMPTY) +#define F_WFREQFIFOEMPTY V_WFREQFIFOEMPTY(1U) + +#define S_RFRESPFIFOEMPTY 10 +#define V_RFRESPFIFOEMPTY(x) ((x) << S_RFRESPFIFOEMPTY) +#define F_RFRESPFIFOEMPTY V_RFRESPFIFOEMPTY(1U) + +#define S_RFREQFIFOEMPTY 9 +#define V_RFREQFIFOEMPTY(x) ((x) << S_RFREQFIFOEMPTY) +#define F_RFREQFIFOEMPTY V_RFREQFIFOEMPTY(1U) + +#define S_PIORESPFIFOLEVEL 7 +#define M_PIORESPFIFOLEVEL 0x3 +#define V_PIORESPFIFOLEVEL(x) ((x) << S_PIORESPFIFOLEVEL) +#define G_PIORESPFIFOLEVEL(x) (((x) >> S_PIORESPFIFOLEVEL) & M_PIORESPFIFOLEVEL) + +#define S_CFRESPFIFOEMPTY 6 +#define V_CFRESPFIFOEMPTY(x) ((x) << S_CFRESPFIFOEMPTY) +#define F_CFRESPFIFOEMPTY V_CFRESPFIFOEMPTY(1U) + +#define S_CFREQFIFOEMPTY 5 +#define V_CFREQFIFOEMPTY(x) ((x) << S_CFREQFIFOEMPTY) +#define F_CFREQFIFOEMPTY V_CFREQFIFOEMPTY(1U) + +#define S_VPDRESPFIFOEMPTY 4 +#define V_VPDRESPFIFOEMPTY(x) ((x) << S_VPDRESPFIFOEMPTY) +#define F_VPDRESPFIFOEMPTY V_VPDRESPFIFOEMPTY(1U) + +#define S_VPDREQFIFOEMPTY 3 +#define V_VPDREQFIFOEMPTY(x) ((x) << S_VPDREQFIFOEMPTY) +#define F_VPDREQFIFOEMPTY V_VPDREQFIFOEMPTY(1U) + +#define S_PIO_RSPPND 2 +#define V_PIO_RSPPND(x) ((x) << S_PIO_RSPPND) +#define F_PIO_RSPPND V_PIO_RSPPND(1U) + +#define S_DLYTRNPND 1 +#define V_DLYTRNPND(x) ((x) << S_DLYTRNPND) +#define F_DLYTRNPND V_DLYTRNPND(1U) + +#define S_SPLTRNPND 0 +#define V_SPLTRNPND(x) ((x) << S_SPLTRNPND) +#define F_SPLTRNPND V_SPLTRNPND(1U) + +#define A_PCIX_STAT1 0x9c + +#define S_WFINIST 26 +#define M_WFINIST 0xf +#define V_WFINIST(x) ((x) << S_WFINIST) +#define G_WFINIST(x) (((x) >> S_WFINIST) & M_WFINIST) + +#define S_ARBST 23 +#define M_ARBST 0x7 +#define V_ARBST(x) ((x) << S_ARBST) +#define G_ARBST(x) (((x) >> S_ARBST) & M_ARBST) + +#define S_PMIST 21 +#define M_PMIST 0x3 +#define V_PMIST(x) ((x) << S_PMIST) +#define G_PMIST(x) (((x) >> S_PMIST) & M_PMIST) + +#define S_CALST 19 +#define M_CALST 0x3 +#define V_CALST(x) ((x) << S_CALST) +#define G_CALST(x) (((x) >> S_CALST) & M_CALST) + +#define S_CFREQRDST 17 +#define M_CFREQRDST 0x3 +#define V_CFREQRDST(x) ((x) << S_CFREQRDST) +#define G_CFREQRDST(x) (((x) >> S_CFREQRDST) & M_CFREQRDST) + +#define S_CFINIST 15 +#define M_CFINIST 0x3 +#define V_CFINIST(x) ((x) << S_CFINIST) +#define G_CFINIST(x) (((x) >> S_CFINIST) & M_CFINIST) + +#define S_CFRESPRDST 13 +#define M_CFRESPRDST 0x3 +#define V_CFRESPRDST(x) ((x) << S_CFRESPRDST) +#define G_CFRESPRDST(x) (((x) >> S_CFRESPRDST) & M_CFRESPRDST) + +#define S_INICST 10 +#define M_INICST 0x7 +#define V_INICST(x) ((x) << S_INICST) +#define G_INICST(x) (((x) >> S_INICST) & M_INICST) + +#define S_INIXST 7 +#define M_INIXST 0x7 +#define V_INIXST(x) ((x) << S_INIXST) +#define G_INIXST(x) (((x) >> S_INIXST) & M_INIXST) + +#define S_INTST 4 +#define M_INTST 0x7 +#define V_INTST(x) ((x) << S_INTST) +#define G_INTST(x) (((x) >> S_INTST) & M_INTST) + +#define S_PIOST 2 +#define M_PIOST 0x3 +#define V_PIOST(x) ((x) << S_PIOST) +#define G_PIOST(x) (((x) >> S_PIOST) & M_PIOST) + +#define S_RFREQRDST 0 +#define M_RFREQRDST 0x3 +#define V_RFREQRDST(x) ((x) << S_RFREQRDST) +#define G_RFREQRDST(x) (((x) >> S_RFREQRDST) & M_RFREQRDST) + /* registers for module PCIE0 */ #define PCIE0_BASE_ADDR 0x80 #define A_PCIE_INT_ENABLE 0x80 -#define S_BISTERR 15 +#define S_BISTERR 19 #define M_BISTERR 0xff #define V_BISTERR(x) ((x) << S_BISTERR) #define G_BISTERR(x) (((x) >> S_BISTERR) & M_BISTERR) +#define S_TXPARERR 18 +#define V_TXPARERR(x) ((x) << S_TXPARERR) +#define F_TXPARERR V_TXPARERR(1U) + +#define S_RXPARERR 17 +#define V_RXPARERR(x) ((x) << S_RXPARERR) +#define F_RXPARERR V_RXPARERR(1U) + +#define S_RETRYLUTPARERR 16 +#define V_RETRYLUTPARERR(x) ((x) << S_RETRYLUTPARERR) +#define F_RETRYLUTPARERR V_RETRYLUTPARERR(1U) + +#define S_RETRYBUFPARERR 15 +#define V_RETRYBUFPARERR(x) ((x) << S_RETRYBUFPARERR) +#define F_RETRYBUFPARERR V_RETRYBUFPARERR(1U) + #define S_PCIE_MSIXPARERR 12 #define M_PCIE_MSIXPARERR 0x7 #define V_PCIE_MSIXPARERR(x) ((x) << S_PCIE_MSIXPARERR) @@ -787,6 +1012,18 @@ #define A_PCIE_INT_CAUSE 0x84 #define A_PCIE_CFG 0x88 +#define S_PCIE_DMASTOPEN 24 +#define V_PCIE_DMASTOPEN(x) ((x) << S_PCIE_DMASTOPEN) +#define F_PCIE_DMASTOPEN V_PCIE_DMASTOPEN(1U) + +#define S_PRIORITYINTA 23 +#define V_PRIORITYINTA(x) ((x) << S_PRIORITYINTA) +#define F_PRIORITYINTA V_PRIORITYINTA(1U) + +#define S_INIFULLPKT 22 +#define V_INIFULLPKT(x) ((x) << S_INIFULLPKT) +#define F_INIFULLPKT V_INIFULLPKT(1U) + #define S_ENABLELINKDWNDRST 21 #define V_ENABLELINKDWNDRST(x) ((x) << S_ENABLELINKDWNDRST) #define F_ENABLELINKDWNDRST V_ENABLELINKDWNDRST(1U) @@ -825,15 +1062,37 @@ #define V_CRSTWRMMODE(x) ((x) << S_CRSTWRMMODE) #define F_CRSTWRMMODE V_CRSTWRMMODE(1U) -#define S_PRIORITYINTA 23 -#define V_PRIORITYINTA(x) ((x) << S_PRIORITYINTA) -#define F_PRIORITYINTA V_PRIORITYINTA(1U) +#define A_PCIE_MODE 0x8c + +#define S_TAR_STATE 29 +#define M_TAR_STATE 0x7 +#define V_TAR_STATE(x) ((x) << S_TAR_STATE) +#define G_TAR_STATE(x) (((x) >> S_TAR_STATE) & M_TAR_STATE) + +#define S_RF_STATEINI 26 +#define M_RF_STATEINI 0x7 +#define V_RF_STATEINI(x) ((x) << S_RF_STATEINI) +#define G_RF_STATEINI(x) (((x) >> S_RF_STATEINI) & M_RF_STATEINI) + +#define S_CF_STATEINI 23 +#define M_CF_STATEINI 0x7 +#define V_CF_STATEINI(x) ((x) << S_CF_STATEINI) +#define G_CF_STATEINI(x) (((x) >> S_CF_STATEINI) & M_CF_STATEINI) + +#define S_PIO_STATEPL 20 +#define M_PIO_STATEPL 0x7 +#define V_PIO_STATEPL(x) ((x) << S_PIO_STATEPL) +#define G_PIO_STATEPL(x) (((x) >> S_PIO_STATEPL) & M_PIO_STATEPL) -#define S_INIFULLPKT 22 -#define V_INIFULLPKT(x) ((x) << S_INIFULLPKT) -#define F_INIFULLPKT V_INIFULLPKT(1U) +#define S_PIO_STATEISC 18 +#define M_PIO_STATEISC 0x3 +#define V_PIO_STATEISC(x) ((x) << S_PIO_STATEISC) +#define G_PIO_STATEISC(x) (((x) >> S_PIO_STATEISC) & M_PIO_STATEISC) -#define A_PCIE_MODE 0x8c +#define S_NUMFSTTRNSEQRX 10 +#define M_NUMFSTTRNSEQRX 0xff +#define V_NUMFSTTRNSEQRX(x) ((x) << S_NUMFSTTRNSEQRX) +#define G_NUMFSTTRNSEQRX(x) (((x) >> S_NUMFSTTRNSEQRX) & M_NUMFSTTRNSEQRX) #define S_LNKCNTLSTATE 2 #define M_LNKCNTLSTATE 0xff @@ -848,10 +1107,76 @@ #define V_LNKINITIAL(x) ((x) << S_LNKINITIAL) #define F_LNKINITIAL V_LNKINITIAL(1U) -#define S_NUMFSTTRNSEQRX 10 -#define M_NUMFSTTRNSEQRX 0xff -#define V_NUMFSTTRNSEQRX(x) ((x) << S_NUMFSTTRNSEQRX) -#define G_NUMFSTTRNSEQRX(x) (((x) >> S_NUMFSTTRNSEQRX) & M_NUMFSTTRNSEQRX) +#define A_PCIE_STAT 0x90 + +#define S_INI_STATE 28 +#define M_INI_STATE 0xf +#define V_INI_STATE(x) ((x) << S_INI_STATE) +#define G_INI_STATE(x) (((x) >> S_INI_STATE) & M_INI_STATE) + +#define S_WF_STATEINI 24 +#define M_WF_STATEINI 0xf +#define V_WF_STATEINI(x) ((x) << S_WF_STATEINI) +#define G_WF_STATEINI(x) (((x) >> S_WF_STATEINI) & M_WF_STATEINI) + +#define S_PLM_REQFIFOCNT 22 +#define M_PLM_REQFIFOCNT 0x3 +#define V_PLM_REQFIFOCNT(x) ((x) << S_PLM_REQFIFOCNT) +#define G_PLM_REQFIFOCNT(x) (((x) >> S_PLM_REQFIFOCNT) & M_PLM_REQFIFOCNT) + +#define S_ER_REQFIFOEMPTY 21 +#define V_ER_REQFIFOEMPTY(x) ((x) << S_ER_REQFIFOEMPTY) +#define F_ER_REQFIFOEMPTY V_ER_REQFIFOEMPTY(1U) + +#define S_WF_RSPFIFOEMPTY 20 +#define V_WF_RSPFIFOEMPTY(x) ((x) << S_WF_RSPFIFOEMPTY) +#define F_WF_RSPFIFOEMPTY V_WF_RSPFIFOEMPTY(1U) + +#define S_WF_REQFIFOEMPTY 19 +#define V_WF_REQFIFOEMPTY(x) ((x) << S_WF_REQFIFOEMPTY) +#define F_WF_REQFIFOEMPTY V_WF_REQFIFOEMPTY(1U) + +#define S_RF_RSPFIFOEMPTY 18 +#define V_RF_RSPFIFOEMPTY(x) ((x) << S_RF_RSPFIFOEMPTY) +#define F_RF_RSPFIFOEMPTY V_RF_RSPFIFOEMPTY(1U) + +#define S_RF_REQFIFOEMPTY 17 +#define V_RF_REQFIFOEMPTY(x) ((x) << S_RF_REQFIFOEMPTY) +#define F_RF_REQFIFOEMPTY V_RF_REQFIFOEMPTY(1U) + +#define S_RF_ACTEMPTY 16 +#define V_RF_ACTEMPTY(x) ((x) << S_RF_ACTEMPTY) +#define F_RF_ACTEMPTY V_RF_ACTEMPTY(1U) + +#define S_PIO_RSPFIFOCNT 11 +#define M_PIO_RSPFIFOCNT 0x1f +#define V_PIO_RSPFIFOCNT(x) ((x) << S_PIO_RSPFIFOCNT) +#define G_PIO_RSPFIFOCNT(x) (((x) >> S_PIO_RSPFIFOCNT) & M_PIO_RSPFIFOCNT) + +#define S_PIO_REQFIFOCNT 5 +#define M_PIO_REQFIFOCNT 0x3f +#define V_PIO_REQFIFOCNT(x) ((x) << S_PIO_REQFIFOCNT) +#define G_PIO_REQFIFOCNT(x) (((x) >> S_PIO_REQFIFOCNT) & M_PIO_REQFIFOCNT) + +#define S_CF_RSPFIFOEMPTY 4 +#define V_CF_RSPFIFOEMPTY(x) ((x) << S_CF_RSPFIFOEMPTY) +#define F_CF_RSPFIFOEMPTY V_CF_RSPFIFOEMPTY(1U) + +#define S_CF_REQFIFOEMPTY 3 +#define V_CF_REQFIFOEMPTY(x) ((x) << S_CF_REQFIFOEMPTY) +#define F_CF_REQFIFOEMPTY V_CF_REQFIFOEMPTY(1U) + +#define S_CF_ACTEMPTY 2 +#define V_CF_ACTEMPTY(x) ((x) << S_CF_ACTEMPTY) +#define F_CF_ACTEMPTY V_CF_ACTEMPTY(1U) + +#define S_VPD_RSPFIFOEMPTY 1 +#define V_VPD_RSPFIFOEMPTY(x) ((x) << S_VPD_RSPFIFOEMPTY) +#define F_VPD_RSPFIFOEMPTY V_VPD_RSPFIFOEMPTY(1U) + +#define S_VPD_REQFIFOEMPTY 0 +#define V_VPD_REQFIFOEMPTY(x) ((x) << S_VPD_REQFIFOEMPTY) +#define F_VPD_REQFIFOEMPTY V_VPD_REQFIFOEMPTY(1U) #define A_PCIE_CAL 0x90 @@ -883,8 +1208,37 @@ #define G_ZIN(x) (((x) >> S_ZIN) & M_ZIN) #define A_PCIE_WOL 0x94 + +#define S_CF_RSPSTATE 12 +#define M_CF_RSPSTATE 0x3 +#define V_CF_RSPSTATE(x) ((x) << S_CF_RSPSTATE) +#define G_CF_RSPSTATE(x) (((x) >> S_CF_RSPSTATE) & M_CF_RSPSTATE) + +#define S_RF_RSPSTATE 10 +#define M_RF_RSPSTATE 0x3 +#define V_RF_RSPSTATE(x) ((x) << S_RF_RSPSTATE) +#define G_RF_RSPSTATE(x) (((x) >> S_RF_RSPSTATE) & M_RF_RSPSTATE) + +#define S_PME_STATE 7 +#define M_PME_STATE 0x7 +#define V_PME_STATE(x) ((x) << S_PME_STATE) +#define G_PME_STATE(x) (((x) >> S_PME_STATE) & M_PME_STATE) + +#define S_INT_STATE 4 +#define M_INT_STATE 0x7 +#define V_INT_STATE(x) ((x) << S_INT_STATE) +#define G_INT_STATE(x) (((x) >> S_INT_STATE) & M_INT_STATE) + #define A_PCIE_PEX_CTRL0 0x98 +#define S_CPLTIMEOUTRETRY 31 +#define V_CPLTIMEOUTRETRY(x) ((x) << S_CPLTIMEOUTRETRY) +#define F_CPLTIMEOUTRETRY V_CPLTIMEOUTRETRY(1U) + +#define S_STRICTTSMN 30 +#define V_STRICTTSMN(x) ((x) << S_STRICTTSMN) +#define F_STRICTTSMN V_STRICTTSMN(1U) + #define S_NUMFSTTRNSEQ 22 #define M_NUMFSTTRNSEQ 0xff #define V_NUMFSTTRNSEQ(x) ((x) << S_NUMFSTTRNSEQ) @@ -903,26 +1257,8 @@ #define V_CPLPNDCHKEN(x) ((x) << S_CPLPNDCHKEN) #define F_CPLPNDCHKEN V_CPLPNDCHKEN(1U) -#define S_CPLTIMEOUTRETRY 31 -#define V_CPLTIMEOUTRETRY(x) ((x) << S_CPLTIMEOUTRETRY) -#define F_CPLTIMEOUTRETRY V_CPLTIMEOUTRETRY(1U) - -#define S_STRICTTSMN 30 -#define V_STRICTTSMN(x) ((x) << S_STRICTTSMN) -#define F_STRICTTSMN V_STRICTTSMN(1U) - #define A_PCIE_PEX_CTRL1 0x9c -#define S_T3A_DLLPTIMEOUTLMT 11 -#define M_T3A_DLLPTIMEOUTLMT 0xfffff -#define V_T3A_DLLPTIMEOUTLMT(x) ((x) << S_T3A_DLLPTIMEOUTLMT) -#define G_T3A_DLLPTIMEOUTLMT(x) (((x) >> S_T3A_DLLPTIMEOUTLMT) & M_T3A_DLLPTIMEOUTLMT) - -#define S_T3A_ACKLAT 0 -#define M_T3A_ACKLAT 0x7ff -#define V_T3A_ACKLAT(x) ((x) << S_T3A_ACKLAT) -#define G_T3A_ACKLAT(x) (((x) >> S_T3A_ACKLAT) & M_T3A_ACKLAT) - #define S_RXPHYERREN 31 #define V_RXPHYERREN(x) ((x) << S_RXPHYERREN) #define F_RXPHYERREN V_RXPHYERREN(1U) @@ -937,34 +1273,48 @@ #define V_ACKLAT(x) ((x) << S_ACKLAT) #define G_ACKLAT(x) (((x) >> S_ACKLAT) & M_ACKLAT) +#define S_T3A_DLLPTIMEOUTLMT 11 +#define M_T3A_DLLPTIMEOUTLMT 0xfffff +#define V_T3A_DLLPTIMEOUTLMT(x) ((x) << S_T3A_DLLPTIMEOUTLMT) +#define G_T3A_DLLPTIMEOUTLMT(x) (((x) >> S_T3A_DLLPTIMEOUTLMT) & M_T3A_DLLPTIMEOUTLMT) + +#define S_T3A_ACKLAT 0 +#define M_T3A_ACKLAT 0x7ff +#define V_T3A_ACKLAT(x) ((x) << S_T3A_ACKLAT) +#define G_T3A_ACKLAT(x) (((x) >> S_T3A_ACKLAT) & M_T3A_ACKLAT) + #define A_PCIE_PEX_CTRL2 0xa0 -#define S_PMEXITL1REQ 29 +#define S_LNKCNTLDETDIR 30 +#define V_LNKCNTLDETDIR(x) ((x) << S_LNKCNTLDETDIR) +#define F_LNKCNTLDETDIR V_LNKCNTLDETDIR(1U) + +#define S_ENTERL1REN 29 +#define V_ENTERL1REN(x) ((x) << S_ENTERL1REN) +#define F_ENTERL1REN V_ENTERL1REN(1U) + +#define S_PMEXITL1REQ 28 #define V_PMEXITL1REQ(x) ((x) << S_PMEXITL1REQ) #define F_PMEXITL1REQ V_PMEXITL1REQ(1U) -#define S_PMTXIDLE 28 +#define S_PMTXIDLE 27 #define V_PMTXIDLE(x) ((x) << S_PMTXIDLE) #define F_PMTXIDLE V_PMTXIDLE(1U) -#define S_PCIMODELOOP 27 +#define S_PCIMODELOOP 26 #define V_PCIMODELOOP(x) ((x) << S_PCIMODELOOP) #define F_PCIMODELOOP V_PCIMODELOOP(1U) -#define S_L1ASPMTXRXL0STIME 15 +#define S_L1ASPMTXRXL0STIME 14 #define M_L1ASPMTXRXL0STIME 0xfff #define V_L1ASPMTXRXL0STIME(x) ((x) << S_L1ASPMTXRXL0STIME) #define G_L1ASPMTXRXL0STIME(x) (((x) >> S_L1ASPMTXRXL0STIME) & M_L1ASPMTXRXL0STIME) -#define S_L0SIDLETIME 4 +#define S_L0SIDLETIME 3 #define M_L0SIDLETIME 0x7ff #define V_L0SIDLETIME(x) ((x) << S_L0SIDLETIME) #define G_L0SIDLETIME(x) (((x) >> S_L0SIDLETIME) & M_L0SIDLETIME) >>> TRUNCATED FOR MAIL (1000 lines) <<<
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