Date: Sun, 13 Jan 2008 04:51:17 GMT From: Warner Losh <imp@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 133161 for review Message-ID: <200801130451.m0D4pHfa060279@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=133161 Change 133161 by imp@imp_mbp on 2008/01/13 04:51:00 Make the juniper locore.S match the mips2 world better. Adopt some code from the mips2 branch and try harder to preserve a0..a3 for platform_init... The juniper code supports SMP, and some of that code uses a0..a2. That needs to be resolved in a future commit. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/mips/locore.S#7 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/locore.S#7 (text+ko) ==== @@ -91,12 +91,53 @@ _C_LABEL(_start): _C_LABEL(btext): VECTOR(_locore, unknown) + /* UNSAFE TO USE a0..a3, since some bootloaders pass that to us */ + # Keep firmware exception handlers until the kernel sets up its own # exception handlers. li v0, SR_BOOT_EXC_VEC mtc0 v0, COP_0_STATUS_REG # Disable interrupts. mtc0 zero, COP_0_CAUSE_REG # Clear soft interrupts + /* + * t0: Bits to preserve if set: + * Soft reset + * Boot exception vectors (firmware-provided) + */ + li t0, (MIPS_SR_BEV | MIPS_SR_SOFT_RESET) + + /* + * t1: Bits to set explicitly: + * Enable FPU + */ + li t1, MIPS_SR_COP_1_BIT + + /* + * Read coprocessor 0 status register, clear bits not + * preserved (namely, clearing interrupt bits), and set + * bits we want to explicitly set. + */ + mfc0 t2, MIPS_COP_0_STATUS + and t2, t0 + or t2, t1 + mtc0 t2, MIPS_COP_0_STATUS + COP0_SYNC + /* Extra nops for the FPU to spin up. */ + + /* Read and store the PrID FPU ID for CPU identification. */ + mfc0 t0, MIPS_COP_0_PRID +#ifndef CPU_NOFPU + cfc1 t1, MIPS_FPU_ID +#else + /* + * This platform has no FPU, and attempting to detect one + * using the official method causes an exception. + */ + li t1, 0x0 +#endif + sw t0, cpu_id + sw t1, fpu_id + /* * Initialize stack and call machine startup. */ @@ -118,10 +159,7 @@ sw a2, cfe_vector /* Firmware entry vector */ no_cfe: #endif - /* reset count register to 1 on each CPU */ - li a0, 1 - mtc0 a0, COP_0_COUNT - nop + /* * Block all the slave CPUs */ @@ -152,24 +190,14 @@ bne a2, zero, start_secondary nop -/*XXXimp: should call platform_start here and also port over the - platform specific code. */ - jal _C_LABEL(mips_init) # mips_init(argc, argv, envp) + /* Call the platform-specific startup code. */ + jal platform_start sw zero, START_FRAME - 8(sp) # Zero out old fp for debugger nop - mfc0 t0, COP_0_STATUS_REG - or t0, SR_COP_1_BIT - mtc0 t0, COP_0_STATUS_REG # enable the fp coprocessor + la sp, _C_LABEL(thread0) lw a0, TD_PCB(sp) subu sp, a0, START_FRAME - nop - nop # wait for new status to - nop - nop - nop # wait for new status to - nop # to be effective - nop mfc0 t1, COP_0_CONFIG, 1 # Check FPU present or not andi t1, 0x1 beqz t1, no_fpu
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