Date: Sat, 16 Nov 1996 16:14:47 +0100 From: se@FreeBSD.org (Stefan Esser) To: bde@zeta.org.au (Bruce Evans) Cc: mrcpu@cdsnet.net, se@FreeBSD.org, hackers@FreeBSD.org Subject: Re: IRQ sharing on PCI? Message-ID: <199611161514.QAA00434@x14.mi.uni-koeln.de> In-Reply-To: <199611161242.XAA17993@godzilla.zeta.org.au>; from Bruce Evans on Nov 16, 1996 23:42:50 %2B1100 References: <199611161242.XAA17993@godzilla.zeta.org.au>
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On Nov 16, bde@zeta.org.au (Bruce Evans) wrote:
> >> None of my other Pentiums do it, they all get different IRQ's.
> >
> >This depends on the PCI BIOS, which is free
> >to assign any IRQ to any PCI Int line.
> >PCI requires shared interrupts to work, since
> >there are far less real interrupt request
> >inputs in a typical system, than independent
> >PCI Int lines.
>
> Doesn't a typical system have only 3 or 4 PCI slots and many more
> than 3 or 4 IRQs, so it is hard to run out of IRQs? Mine has 3
> PCI slots, all full (:-(), and they get assigned irqs 10, 11 and
> 12 (one wasted for vga0).
No, PCI supports 4 individual interrupt lines per slot,
so you'd need 12 IRQs to cover all of them. Your VGA card
most probably got an IRQ assigned, because it announced to
be using Int A. A current PCI BIOS will assign IRQs to all
slots that are occupied by a device, which has a non-zero
value in its interrupt pin config PCI space register.
(Try the following sequence of commands on a -current system:
# pciconf -l
pci0:0:0: class=0x000000 card=0x00000000 chip=0x04838086 rev=0x04 hdr=0x00
pci0:1:0: class=0x000000 card=0x00000000 chip=0x00011000 rev=0x01 hdr=0x00
pci0:2:0: class=0x000000 card=0x00000000 chip=0x04848086 rev=0x03 hdr=0x00
pci0:4:0: class=0x010000 card=0x00000000 chip=0x000f1000 rev=0x01 hdr=0x00
pci0:5:0: class=0x000100 card=0x00000000 chip=0x88c15333 rev=0x00 hdr=0x00
pci0:6:0: class=0x020000 card=0x00000000 chip=0x802910ec rev=0x00 hdr=0x00
# pciconf -r pci0:5:0 0x3c # my VGA doesn't have an int pin
0x00000000
# pciconf -r pci0:4:0 0x3c # but my NCR SCSI chip does ... :)
0x4008010c
^^
A 01 means Int A, 02 Int B, and so on ...)
Most PCI chips only use Int A, but a multi-function chip
will use B for the second "function" (identical to a LUN
in SCSI terms), C to the third, ... , A again to the fifth,
and so on.
A PCI to PCI bridge will connect Int A to D of secondary
bus slot 0 to Int A to D on its slot on the primary bus,
Int A to D of slot 1 to Int B to D and then wrap around to
Int A, and so on. (BTW: for cascaded PCI to PCI bridges
apply resursively ;)
This means that there are in fact four PCI Int lines, but
most PCI cards will only use Int A. multi-function devices
will use Int A and Int B, if two functions are implemented
(see the AMD SCSI+Ethernet Combo chip), or all four lines
if there are four functions on a chip (announced 4 channel
Ethernet cards). And if you are using a PCI to PCI bridge
(current 4 channel Ethernet cards and the AH3940 or PCI bus
extender boxes, for example), then the PCI Int lines used
will depend on the slots used on the secondary side of the
PCI bridge. (The scheme used is meant to randomize PCI Int
lines used and to reduce the probability of shared interrupt
lines. But those must be supported anyway ...)
Regards, STefan
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