Date: Tue, 19 May 2009 02:43:21 +0000 (UTC) From: Oleksandr Tymoshenko <gonzo@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r192364 - projects/mips/sys/mips/mips Message-ID: <200905190243.n4J2hLHh082407@svn.freebsd.org>
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Author: gonzo Date: Tue May 19 02:43:21 2009 New Revision: 192364 URL: http://svn.freebsd.org/changeset/base/192364 Log: - Cleanup ticker initialization code. For some MIPS cpu Counter register increments only every second cycle. The only timing references for us is Count value. Therefore it's better to convert frequencies related to it and use them. Besides cleanup this commit fixes twice more then requested sleep interval problem. Modified: projects/mips/sys/mips/mips/tick.c Modified: projects/mips/sys/mips/mips/tick.c ============================================================================== --- projects/mips/sys/mips/mips/tick.c Tue May 19 01:58:00 2009 (r192363) +++ projects/mips/sys/mips/mips/tick.c Tue May 19 02:43:21 2009 (r192364) @@ -138,25 +138,19 @@ mips_timer_init_params(uint64_t platform * function should be called before cninit. */ counter_freq = platform_counter_freq; + /* + * XXX: Some MIPS32 cores update the Count register only every two + * pipeline cycles. + */ + if (double_count != 0) + counter_freq /= 2; + cycles_per_tick = counter_freq / 1000; - if (double_count) - cycles_per_tick *= 2; cycles_per_hz = counter_freq / hz; cycles_per_usec = counter_freq / (1 * 1000 * 1000); cycles_per_sec = counter_freq ; counter_timecounter.tc_frequency = counter_freq; - /* - * XXX: Some MIPS32 cores update the Count register only every two - * pipeline cycles. - * XXX2: We can read this from the hardware register on some - * systems. Need to investigate. - */ - if (double_count != 0) { - cycles_per_hz /= 2; - cycles_per_usec /= 2; - cycles_per_sec /= 2; - } printf("hz=%d cyl_per_hz:%jd cyl_per_usec:%jd freq:%jd cyl_per_hz:%jd cyl_per_sec:%jd\n", hz, cycles_per_tick, @@ -346,6 +340,7 @@ clock_attach(device_t dev) device_printf(dev, "bus_setup_intr returned %d\n", error); return (error); } + mips_wr_compare(mips_rd_count() + counter_freq / hz); return (0); }
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