Date: Thu, 5 Jul 2007 11:49:18 -0700 (PDT) From: Neelkanth Natu <neelnatu@yahoo.com> To: freebsd-mips@freebsd.org Subject: Fwd: p4-projects Digest, Vol 209, Issue 11 Message-ID: <755925.61959.qm@web34414.mail.mud.yahoo.com>
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Hi Oleksandr, When do you see this Address Error exception? I would not expect this to happen as a result of a fork() called from userland because the status register you restore will have the EXL bit set (since you inherited it from the parent's trap frame). And as long as the EXL bit is set you are still in the kernel mode irrespective of the KSU field. One place where you might see this is when init is going into usermode for the very first time. If that is where you get the exception then the right way to fix is to set the EXL bit in exec_setregs() in machdep.c. That way you don't need duplicate code in fork_trampoline() and exception_restore_registers(). best Neel > ------------------------------ > > Message: 3 > Date: Thu, 5 Jul 2007 11:18:29 GMT > From: Oleksandr Tymoshenko <gonzo@FreeBSD.org> > Subject: PERFORCE change 122941 for review > To: Perforce Change Reviews <perforce@FreeBSD.org> > Message-ID: <200707051118.l65BITOC049552@repoman.freebsd.org> > > http://perforce.freebsd.org/chv.cgi?CH=122941 > > Change 122941 by gonzo@gonzo_jeeves on 2007/07/05 11:17:52 > > o Replace exception_restore_registers with it's content and put > setting cp0 status register to delay slot of eret. Otherwise > we're getting Address Error exception trying to fetch eret > instruction with KSU bit set in status register. > > Affected files ... > > .. //depot/projects/mips2/src/sys/mips/mips/swtch.S#12 edit > > Differences ... > > ==== //depot/projects/mips2/src/sys/mips/mips/swtch.S#12 (text+ko) ==== > > @@ -193,7 +193,67 @@ > .set noat > lw t3, PC_CURTHREAD(t2) > lw k1, TD_FRAME(t3) > - jal exception_restore_registers > - nop > + > + /* > + * Load extended registers into some GPRs, and start unrolling > + * the trapframe, putting back the extended registers just > + * before we need to restore those GPRs. This doesn't do any > + * special ordering like the save_registers routine might, > + * but it keeps the flow relatively consistent. > + */ > + lw a1, TF_REG_EPC(k1) > + lw a0, TF_REG_MULHI(k1) > + lw v1, TF_REG_MULLO(k1) > + > + lw ra, TF_REG_RA(k1) > + lw t9, TF_REG_T9(k1) > + lw t8, TF_REG_T8(k1) > + lw ta3, TF_REG_TA3(k1) > + lw ta2, TF_REG_TA2(k1) > + lw ta1, TF_REG_TA1(k1) > + lw ta0, TF_REG_TA0(k1) > + lw t3, TF_REG_T3(k1) > + lw t2, TF_REG_T2(k1) > + lw t1, TF_REG_T1(k1) > + lw t0, TF_REG_T0(k1) > + > + lw s0, TF_REG_S0(k1) > + lw s1, TF_REG_S1(k1) > + lw s2, TF_REG_S2(k1) > + lw s3, TF_REG_S3(k1) > + lw s4, TF_REG_S4(k1) > + lw s5, TF_REG_S5(k1) > + lw s6, TF_REG_S6(k1) > + lw s7, TF_REG_S7(k1) > + lw s8, TF_REG_S8(k1) > + > + /* > + * Brief interlude. > + */ > + mtc0 a1, MIPS_COP_0_EXC_PC > + mthi a0 > + mtlo v1 > + > + /* > + * Now restore the registers we used for scratch, and nearby > + * GPRs. > + */ > + lw a3, TF_REG_A3(k1) > + lw a2, TF_REG_A2(k1) > + lw a1, TF_REG_A1(k1) > + lw a0, TF_REG_A0(k1) > + lw v1, TF_REG_V1(k1) > + lw v0, TF_REG_V0(k1) > + lw gp, TF_REG_GP(k1) > + lw sp, TF_REG_SP(k1) > + > + /* > + * We are done with the assembler temporary, restore it, and > + * return with it disabled, just in case. > + */ > + .set noat > + lw AT, TF_REG_AST(k1) > + lw k1, TF_REG_SR(k1) > eret > + mtc0 k1, MIPS_COP_0_STATUS > END(fork_trampoline) > > > ------------------------------ > > _______________________________________________ > p4-projects@freebsd.org mailing list > http://lists.freebsd.org/mailman/listinfo/p4-projects > To unsubscribe, send any mail to "p4-projects-unsubscribe@freebsd.org" > > > End of p4-projects Digest, Vol 209, Issue 11 > ******************************************** > ____________________________________________________________________________________ Now that's room service! Choose from over 150,000 hotels in 45,000 destinations on Yahoo! Travel to find your fit. http://farechase.yahoo.com/promo-generic-14795097
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