Date: Sun, 9 Dec 2018 11:36:05 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r341763 - in projects/clang700-import: contrib/libc++/src/filesystem contrib/llvm/include/llvm/DebugInfo/PDB/Native contrib/llvm/include/llvm/ExecutionEngine/Orc contrib/llvm/include/ll... Message-ID: <201812091136.wB9Ba5So014940@repo.freebsd.org>
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Author: dim Date: Sun Dec 9 11:36:04 2018 New Revision: 341763 URL: https://svnweb.freebsd.org/changeset/base/341763 Log: Merge llvm, clang, lld, lldb, compiler-rt and libc++ release_70 branch r348686 (effectively 7.0.1 rc3), resolve conflicts, and bump version numbers. PR: 230240, 230355 Modified: projects/clang700-import/contrib/libc++/src/filesystem/operations.cpp projects/clang700-import/contrib/llvm/include/llvm/DebugInfo/PDB/Native/GlobalsStream.h projects/clang700-import/contrib/llvm/include/llvm/DebugInfo/PDB/Native/ModuleDebugStream.h projects/clang700-import/contrib/llvm/include/llvm/ExecutionEngine/Orc/Core.h projects/clang700-import/contrib/llvm/include/llvm/ExecutionEngine/Orc/OrcRemoteTargetClient.h projects/clang700-import/contrib/llvm/include/llvm/MC/MCAsmBackend.h projects/clang700-import/contrib/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h projects/clang700-import/contrib/llvm/include/llvm/Support/GenericDomTreeConstruction.h projects/clang700-import/contrib/llvm/include/llvm/Transforms/Utils/SSAUpdater.h projects/clang700-import/contrib/llvm/include/llvm/Transforms/Utils/SSAUpdaterImpl.h projects/clang700-import/contrib/llvm/lib/Analysis/MemorySSA.cpp projects/clang700-import/contrib/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp projects/clang700-import/contrib/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp projects/clang700-import/contrib/llvm/lib/MC/MCExpr.cpp projects/clang700-import/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp projects/clang700-import/contrib/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp projects/clang700-import/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp projects/clang700-import/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h projects/clang700-import/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp projects/clang700-import/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h projects/clang700-import/contrib/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td projects/clang700-import/contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td projects/clang700-import/contrib/llvm/lib/Target/Mips/Mips64r6InstrInfo.td projects/clang700-import/contrib/llvm/lib/Target/Mips/MipsFastISel.cpp projects/clang700-import/contrib/llvm/lib/Target/Mips/MipsInstrFPU.td projects/clang700-import/contrib/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp projects/clang700-import/contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp projects/clang700-import/contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp projects/clang700-import/contrib/llvm/lib/Target/PowerPC/P9InstrResources.td projects/clang700-import/contrib/llvm/lib/Target/PowerPC/PPCISelLowering.cpp projects/clang700-import/contrib/llvm/lib/Target/PowerPC/PPCInstrVSX.td projects/clang700-import/contrib/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp projects/clang700-import/contrib/llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp projects/clang700-import/contrib/llvm/lib/Transforms/Utils/LCSSA.cpp projects/clang700-import/contrib/llvm/lib/Transforms/Utils/SSAUpdater.cpp projects/clang700-import/contrib/llvm/tools/clang/include/clang/AST/DeclBase.h projects/clang700-import/contrib/llvm/tools/clang/include/clang/Basic/Attr.td projects/clang700-import/contrib/llvm/tools/clang/include/clang/Basic/AttrDocs.td projects/clang700-import/contrib/llvm/tools/clang/include/clang/Basic/DiagnosticFrontendKinds.td projects/clang700-import/contrib/llvm/tools/clang/include/clang/Basic/DiagnosticSemaKinds.td projects/clang700-import/contrib/llvm/tools/clang/lib/AST/ASTContext.cpp projects/clang700-import/contrib/llvm/tools/clang/lib/AST/Decl.cpp projects/clang700-import/contrib/llvm/tools/clang/lib/CodeGen/CodeGenFunction.cpp projects/clang700-import/contrib/llvm/tools/clang/lib/CodeGen/CodeGenFunction.h projects/clang700-import/contrib/llvm/tools/clang/lib/CodeGen/CodeGenModule.cpp projects/clang700-import/contrib/llvm/tools/clang/lib/CodeGen/CoverageMappingGen.cpp projects/clang700-import/contrib/llvm/tools/clang/lib/Driver/ToolChains/Arch/PPC.cpp projects/clang700-import/contrib/llvm/tools/clang/lib/Driver/ToolChains/Arch/PPC.h projects/clang700-import/contrib/llvm/tools/clang/lib/Driver/ToolChains/OpenBSD.cpp projects/clang700-import/contrib/llvm/tools/clang/lib/Headers/altivec.h projects/clang700-import/contrib/llvm/tools/clang/lib/Sema/SemaInit.cpp projects/clang700-import/contrib/llvm/tools/clang/lib/Serialization/ASTWriter.cpp projects/clang700-import/contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/SimpleSValBuilder.cpp projects/clang700-import/contrib/llvm/tools/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp projects/clang700-import/lib/clang/include/clang/Basic/Version.inc projects/clang700-import/lib/clang/include/lld/Common/Version.inc projects/clang700-import/lib/clang/include/llvm/Support/VCSRevision.h Directory Properties: projects/clang700-import/contrib/compiler-rt/ (props changed) projects/clang700-import/contrib/libc++/ (props changed) projects/clang700-import/contrib/llvm/ (props changed) projects/clang700-import/contrib/llvm/tools/clang/ (props changed) projects/clang700-import/contrib/llvm/tools/lld/ (props changed) projects/clang700-import/contrib/llvm/tools/lldb/ (props changed) Modified: projects/clang700-import/contrib/libc++/src/filesystem/operations.cpp ============================================================================== --- projects/clang700-import/contrib/libc++/src/filesystem/operations.cpp Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/libc++/src/filesystem/operations.cpp Sun Dec 9 11:36:04 2018 (r341763) @@ -352,7 +352,6 @@ struct FileDescriptor { ~FileDescriptor() { close(); } - FileDescriptor() = default; FileDescriptor(FileDescriptor const&) = delete; FileDescriptor& operator=(FileDescriptor const&) = delete; Modified: projects/clang700-import/contrib/llvm/include/llvm/DebugInfo/PDB/Native/GlobalsStream.h ============================================================================== --- projects/clang700-import/contrib/llvm/include/llvm/DebugInfo/PDB/Native/GlobalsStream.h Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/include/llvm/DebugInfo/PDB/Native/GlobalsStream.h Sun Dec 9 11:36:04 2018 (r341763) @@ -30,8 +30,6 @@ class GSIHashIterator GSIHashIterator, FixedStreamArrayIterator<PSHashRecord>, std::random_access_iterator_tag, const uint32_t> { public: - GSIHashIterator() = default; - template <typename T> GSIHashIterator(T &&v) : GSIHashIterator::iterator_adaptor_base(std::forward<T &&>(v)) {} Modified: projects/clang700-import/contrib/llvm/include/llvm/DebugInfo/PDB/Native/ModuleDebugStream.h ============================================================================== --- projects/clang700-import/contrib/llvm/include/llvm/DebugInfo/PDB/Native/ModuleDebugStream.h Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/include/llvm/DebugInfo/PDB/Native/ModuleDebugStream.h Sun Dec 9 11:36:04 2018 (r341763) @@ -49,7 +49,7 @@ class ModuleDebugStreamRef { (public) BinarySubstreamRef getC13LinesSubstream() const; BinarySubstreamRef getGlobalRefsSubstream() const; - ModuleDebugStreamRef &operator=(ModuleDebugStreamRef &&Other) = default; + ModuleDebugStreamRef &operator=(ModuleDebugStreamRef &&Other) = delete; iterator_range<DebugSubsectionIterator> subsections() const; codeview::DebugSubsectionArray getSubsectionsArray() const { Modified: projects/clang700-import/contrib/llvm/include/llvm/ExecutionEngine/Orc/Core.h ============================================================================== --- projects/clang700-import/contrib/llvm/include/llvm/ExecutionEngine/Orc/Core.h Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/include/llvm/ExecutionEngine/Orc/Core.h Sun Dec 9 11:36:04 2018 (r341763) @@ -126,7 +126,7 @@ class MaterializationResponsibility { public: MaterializationResponsibility(MaterializationResponsibility &&) = default; MaterializationResponsibility & - operator=(MaterializationResponsibility &&) = default; + operator=(MaterializationResponsibility &&) = delete; /// Destruct a MaterializationResponsibility instance. In debug mode /// this asserts that all symbols being tracked have been either Modified: projects/clang700-import/contrib/llvm/include/llvm/ExecutionEngine/Orc/OrcRemoteTargetClient.h ============================================================================== --- projects/clang700-import/contrib/llvm/include/llvm/ExecutionEngine/Orc/OrcRemoteTargetClient.h Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/include/llvm/ExecutionEngine/Orc/OrcRemoteTargetClient.h Sun Dec 9 11:36:04 2018 (r341763) @@ -70,8 +70,7 @@ class OrcRemoteTargetClient (public) RemoteRTDyldMemoryManager & operator=(const RemoteRTDyldMemoryManager &) = delete; RemoteRTDyldMemoryManager(RemoteRTDyldMemoryManager &&) = default; - RemoteRTDyldMemoryManager & - operator=(RemoteRTDyldMemoryManager &&) = default; + RemoteRTDyldMemoryManager &operator=(RemoteRTDyldMemoryManager &&) = delete; uint8_t *allocateCodeSection(uintptr_t Size, unsigned Alignment, unsigned SectionID, Modified: projects/clang700-import/contrib/llvm/include/llvm/MC/MCAsmBackend.h ============================================================================== --- projects/clang700-import/contrib/llvm/include/llvm/MC/MCAsmBackend.h Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/include/llvm/MC/MCAsmBackend.h Sun Dec 9 11:36:04 2018 (r341763) @@ -165,6 +165,11 @@ class MCAsmBackend { (public) return 0; } + /// Check whether a given symbol has been flagged with MICROMIPS flag. + virtual bool isMicroMips(const MCSymbol *Sym) const { + return false; + } + /// Handles all target related code padding when starting to write a new /// basic block to an object file. /// Modified: projects/clang700-import/contrib/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h ============================================================================== --- projects/clang700-import/contrib/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h Sun Dec 9 11:36:04 2018 (r341763) @@ -641,8 +641,6 @@ class LineCoverageIterator (public) this->operator++(); } - LineCoverageIterator &operator=(const LineCoverageIterator &R) = default; - bool operator==(const LineCoverageIterator &R) const { return &CD == &R.CD && Next == R.Next && Ended == R.Ended; } Modified: projects/clang700-import/contrib/llvm/include/llvm/Support/GenericDomTreeConstruction.h ============================================================================== --- projects/clang700-import/contrib/llvm/include/llvm/Support/GenericDomTreeConstruction.h Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/include/llvm/Support/GenericDomTreeConstruction.h Sun Dec 9 11:36:04 2018 (r341763) @@ -1186,6 +1186,20 @@ struct SemiNCAInfo { << '\t' << U << "\n"); LLVM_DEBUG(dbgs() << "\n"); + // Recalculate the DominatorTree when the number of updates + // exceeds a threshold, which usually makes direct updating slower than + // recalculation. We select this threshold proportional to the + // size of the DominatorTree. The constant is selected + // by choosing the one with an acceptable performance on some real-world + // inputs. + + // Make unittests of the incremental algorithm work + if (DT.DomTreeNodes.size() <= 100) { + if (NumLegalized > DT.DomTreeNodes.size()) + CalculateFromScratch(DT, &BUI); + } else if (NumLegalized > DT.DomTreeNodes.size() / 40) + CalculateFromScratch(DT, &BUI); + // If the DominatorTree was recalculated at some point, stop the batch // updates. Full recalculations ignore batch updates and look at the actual // CFG. Modified: projects/clang700-import/contrib/llvm/include/llvm/Transforms/Utils/SSAUpdater.h ============================================================================== --- projects/clang700-import/contrib/llvm/include/llvm/Transforms/Utils/SSAUpdater.h Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/include/llvm/Transforms/Utils/SSAUpdater.h Sun Dec 9 11:36:04 2018 (r341763) @@ -76,6 +76,10 @@ class SSAUpdater { (public) /// block. bool HasValueForBlock(BasicBlock *BB) const; + /// Return the value for the specified block if the SSAUpdater has one, + /// otherwise return nullptr. + Value *FindValueForBlock(BasicBlock *BB) const; + /// Construct SSA form, materializing a value that is live at the end /// of the specified block. Value *GetValueAtEndOfBlock(BasicBlock *BB); Modified: projects/clang700-import/contrib/llvm/include/llvm/Transforms/Utils/SSAUpdaterImpl.h ============================================================================== --- projects/clang700-import/contrib/llvm/include/llvm/Transforms/Utils/SSAUpdaterImpl.h Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/include/llvm/Transforms/Utils/SSAUpdaterImpl.h Sun Dec 9 11:36:04 2018 (r341763) @@ -357,10 +357,9 @@ class SSAUpdaterImpl { (public) BBInfo *Info = *I; if (Info->DefBB != Info) { - // Record the available value at join nodes to speed up subsequent - // uses of this SSAUpdater for the same value. - if (Info->NumPreds > 1) - (*AvailableVals)[Info->BB] = Info->DefBB->AvailableVal; + // Record the available value to speed up subsequent uses of this + // SSAUpdater for the same value. + (*AvailableVals)[Info->BB] = Info->DefBB->AvailableVal; continue; } Modified: projects/clang700-import/contrib/llvm/lib/Analysis/MemorySSA.cpp ============================================================================== --- projects/clang700-import/contrib/llvm/lib/Analysis/MemorySSA.cpp Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/Analysis/MemorySSA.cpp Sun Dec 9 11:36:04 2018 (r341763) @@ -119,7 +119,6 @@ class MemoryLocOrCall { public: bool IsCall = false; - MemoryLocOrCall() = default; MemoryLocOrCall(MemoryUseOrDef *MUD) : MemoryLocOrCall(MUD->getMemoryInst()) {} MemoryLocOrCall(const MemoryUseOrDef *MUD) Modified: projects/clang700-import/contrib/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp ============================================================================== --- projects/clang700-import/contrib/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Sun Dec 9 11:36:04 2018 (r341763) @@ -1156,10 +1156,11 @@ MCSection *TargetLoweringObjectFileCOFF::SelectSection MCSymbol *Sym = TM.getSymbol(ComdatGV); StringRef COMDATSymName = Sym->getName(); - // Append "$symbol" to the section name when targetting mingw. The ld.bfd + // Append "$symbol" to the section name *before* IR-level mangling is + // applied when targetting mingw. This is what GCC does, and the ld.bfd // COFF linker will not properly handle comdats otherwise. if (getTargetTriple().isWindowsGNUEnvironment()) - raw_svector_ostream(Name) << '$' << COMDATSymName; + raw_svector_ostream(Name) << '$' << ComdatGV->getName(); return getContext().getCOFFSection(Name, Characteristics, Kind, COMDATSymName, Selection, UniqueID); Modified: projects/clang700-import/contrib/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp ============================================================================== --- projects/clang700-import/contrib/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp Sun Dec 9 11:36:04 2018 (r341763) @@ -275,7 +275,7 @@ RuntimeDyldImpl::loadObjectImpl(const object::ObjectFi uint64_t Size = I->getCommonSize(); if (!CommonAlign) CommonAlign = Align; - CommonSize += alignTo(CommonSize, Align) + Size; + CommonSize = alignTo(CommonSize, Align) + Size; CommonSymbolsToAllocate.push_back(*I); } } else Modified: projects/clang700-import/contrib/llvm/lib/MC/MCExpr.cpp ============================================================================== --- projects/clang700-import/contrib/llvm/lib/MC/MCExpr.cpp Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/MC/MCExpr.cpp Sun Dec 9 11:36:04 2018 (r341763) @@ -524,6 +524,11 @@ static void AttemptToFoldSymbolOffsetDifference( if (Asm->isThumbFunc(&SA)) Addend |= 1; + // If symbol is labeled as micromips, we set low-bit to ensure + // correct offset in .gcc_except_table + if (Asm->getBackend().isMicroMips(&SA)) + Addend |= 1; + // Clear the symbol expr pointers to indicate we have folded these // operands. A = B = nullptr; Modified: projects/clang700-import/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp ============================================================================== --- projects/clang700-import/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp Sun Dec 9 11:36:04 2018 (r341763) @@ -1515,39 +1515,50 @@ static SDValue emitComparison(SDValue LHS, SDValue RHS /// The CCMP/CCMN/FCCMP/FCCMPE instructions allow the conditional execution of /// a comparison. They set the NZCV flags to a predefined value if their /// predicate is false. This allows to express arbitrary conjunctions, for -/// example "cmp 0 (and (setCA (cmp A)) (setCB (cmp B))))" +/// example "cmp 0 (and (setCA (cmp A)) (setCB (cmp B)))" /// expressed as: /// cmp A /// ccmp B, inv(CB), CA /// check for CB flags /// -/// In general we can create code for arbitrary "... (and (and A B) C)" -/// sequences. We can also implement some "or" expressions, because "(or A B)" -/// is equivalent to "not (and (not A) (not B))" and we can implement some -/// negation operations: -/// We can negate the results of a single comparison by inverting the flags -/// used when the predicate fails and inverting the flags tested in the next -/// instruction; We can also negate the results of the whole previous -/// conditional compare sequence by inverting the flags tested in the next -/// instruction. However there is no way to negate the result of a partial -/// sequence. +/// This naturally lets us implement chains of AND operations with SETCC +/// operands. And we can even implement some other situations by transforming +/// them: +/// - We can implement (NEG SETCC) i.e. negating a single comparison by +/// negating the flags used in a CCMP/FCCMP operations. +/// - We can negate the result of a whole chain of CMP/CCMP/FCCMP operations +/// by negating the flags we test for afterwards. i.e. +/// NEG (CMP CCMP CCCMP ...) can be implemented. +/// - Note that we can only ever negate all previously processed results. +/// What we can not implement by flipping the flags to test is a negation +/// of two sub-trees (because the negation affects all sub-trees emitted so +/// far, so the 2nd sub-tree we emit would also affect the first). +/// With those tools we can implement some OR operations: +/// - (OR (SETCC A) (SETCC B)) can be implemented via: +/// NEG (AND (NEG (SETCC A)) (NEG (SETCC B))) +/// - After transforming OR to NEG/AND combinations we may be able to use NEG +/// elimination rules from earlier to implement the whole thing as a +/// CCMP/FCCMP chain. /// -/// Therefore on encountering an "or" expression we can negate the subtree on -/// one side and have to be able to push the negate to the leafs of the subtree -/// on the other side (see also the comments in code). As complete example: -/// "or (or (setCA (cmp A)) (setCB (cmp B))) -/// (and (setCC (cmp C)) (setCD (cmp D)))" -/// is transformed to -/// "not (and (not (and (setCC (cmp C)) (setCC (cmp D)))) -/// (and (not (setCA (cmp A)) (not (setCB (cmp B))))))" -/// and implemented as: +/// As complete example: +/// or (or (setCA (cmp A)) (setCB (cmp B))) +/// (and (setCC (cmp C)) (setCD (cmp D)))" +/// can be reassociated to: +/// or (and (setCC (cmp C)) setCD (cmp D)) +// (or (setCA (cmp A)) (setCB (cmp B))) +/// can be transformed to: +/// not (and (not (and (setCC (cmp C)) (setCD (cmp D)))) +/// (and (not (setCA (cmp A)) (not (setCB (cmp B))))))" +/// which can be implemented as: /// cmp C /// ccmp D, inv(CD), CC /// ccmp A, CA, inv(CD) /// ccmp B, CB, inv(CA) /// check for CB flags -/// A counterexample is "or (and A B) (and C D)" which cannot be implemented -/// by conditional compare sequences. +/// +/// A counterexample is "or (and A B) (and C D)" which translates to +/// not (and (not (and (not A) (not B))) (not (and (not C) (not D)))), we +/// can only implement 1 of the inner (not) operations, but not both! /// @{ /// Create a conditional comparison; Use CCMP, CCMN or FCCMP as appropriate. @@ -1585,14 +1596,23 @@ static SDValue emitConditionalComparison(SDValue LHS, return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp); } -/// Returns true if @p Val is a tree of AND/OR/SETCC operations. -/// CanPushNegate is set to true if we can push a negate operation through -/// the tree in a was that we are left with AND operations and negate operations -/// at the leafs only. i.e. "not (or (or x y) z)" can be changed to -/// "and (and (not x) (not y)) (not z)"; "not (or (and x y) z)" cannot be -/// brought into such a form. -static bool isConjunctionDisjunctionTree(const SDValue Val, bool &CanNegate, - unsigned Depth = 0) { +/// Returns true if @p Val is a tree of AND/OR/SETCC operations that can be +/// expressed as a conjunction. See \ref AArch64CCMP. +/// \param CanNegate Set to true if we can negate the whole sub-tree just by +/// changing the conditions on the SETCC tests. +/// (this means we can call emitConjunctionRec() with +/// Negate==true on this sub-tree) +/// \param MustBeFirst Set to true if this subtree needs to be negated and we +/// cannot do the negation naturally. We are required to +/// emit the subtree first in this case. +/// \param WillNegate Is true if are called when the result of this +/// subexpression must be negated. This happens when the +/// outer expression is an OR. We can use this fact to know +/// that we have a double negation (or (or ...) ...) that +/// can be implemented for free. +static bool canEmitConjunction(const SDValue Val, bool &CanNegate, + bool &MustBeFirst, bool WillNegate, + unsigned Depth = 0) { if (!Val.hasOneUse()) return false; unsigned Opcode = Val->getOpcode(); @@ -1600,39 +1620,44 @@ static bool isConjunctionDisjunctionTree(const SDValue if (Val->getOperand(0).getValueType() == MVT::f128) return false; CanNegate = true; + MustBeFirst = false; return true; } // Protect against exponential runtime and stack overflow. if (Depth > 6) return false; if (Opcode == ISD::AND || Opcode == ISD::OR) { + bool IsOR = Opcode == ISD::OR; SDValue O0 = Val->getOperand(0); SDValue O1 = Val->getOperand(1); bool CanNegateL; - if (!isConjunctionDisjunctionTree(O0, CanNegateL, Depth+1)) + bool MustBeFirstL; + if (!canEmitConjunction(O0, CanNegateL, MustBeFirstL, IsOR, Depth+1)) return false; bool CanNegateR; - if (!isConjunctionDisjunctionTree(O1, CanNegateR, Depth+1)) + bool MustBeFirstR; + if (!canEmitConjunction(O1, CanNegateR, MustBeFirstR, IsOR, Depth+1)) return false; - if (Opcode == ISD::OR) { - // For an OR expression we need to be able to negate at least one side or - // we cannot do the transformation at all. + if (MustBeFirstL && MustBeFirstR) + return false; + + if (IsOR) { + // For an OR expression we need to be able to naturally negate at least + // one side or we cannot do the transformation at all. if (!CanNegateL && !CanNegateR) return false; - // We can however change a (not (or x y)) to (and (not x) (not y)) if we - // can negate the x and y subtrees. - CanNegate = CanNegateL && CanNegateR; + // If we the result of the OR will be negated and we can naturally negate + // the leafs, then this sub-tree as a whole negates naturally. + CanNegate = WillNegate && CanNegateL && CanNegateR; + // If we cannot naturally negate the whole sub-tree, then this must be + // emitted first. + MustBeFirst = !CanNegate; } else { - // If the operands are OR expressions then we finally need to negate their - // outputs, we can only do that for the operand with emitted last by - // negating OutCC, not for both operands. - bool NeedsNegOutL = O0->getOpcode() == ISD::OR; - bool NeedsNegOutR = O1->getOpcode() == ISD::OR; - if (NeedsNegOutL && NeedsNegOutR) - return false; - // We cannot negate an AND operation (it would become an OR), + assert(Opcode == ISD::AND && "Must be OR or AND"); + // We cannot naturally negate an AND operation. CanNegate = false; + MustBeFirst = MustBeFirstL || MustBeFirstR; } return true; } @@ -1645,11 +1670,9 @@ static bool isConjunctionDisjunctionTree(const SDValue /// and conditional compare operations. @returns an NZCV flags producing node /// and sets @p OutCC to the flags that should be tested or returns SDValue() if /// transformation was not possible. -/// On recursive invocations @p PushNegate may be set to true to have negation -/// effects pushed to the tree leafs; @p Predicate is an NZCV flag predicate -/// for the comparisons in the current subtree; @p Depth limits the search -/// depth to avoid stack overflow. -static SDValue emitConjunctionDisjunctionTreeRec(SelectionDAG &DAG, SDValue Val, +/// \p Negate is true if we want this sub-tree being negated just by changing +/// SETCC conditions. +static SDValue emitConjunctionRec(SelectionDAG &DAG, SDValue Val, AArch64CC::CondCode &OutCC, bool Negate, SDValue CCOp, AArch64CC::CondCode Predicate) { // We're at a tree leaf, produce a conditional comparison operation. @@ -1690,76 +1713,85 @@ static SDValue emitConjunctionDisjunctionTreeRec(Selec return emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate, OutCC, DL, DAG); } - assert((Opcode == ISD::AND || (Opcode == ISD::OR && Val->hasOneUse())) && - "Valid conjunction/disjunction tree"); + assert(Val->hasOneUse() && "Valid conjunction/disjunction tree"); - // Check if both sides can be transformed. + bool IsOR = Opcode == ISD::OR; + SDValue LHS = Val->getOperand(0); + bool CanNegateL; + bool MustBeFirstL; + bool ValidL = canEmitConjunction(LHS, CanNegateL, MustBeFirstL, IsOR); + assert(ValidL && "Valid conjunction/disjunction tree"); + (void)ValidL; + SDValue RHS = Val->getOperand(1); + bool CanNegateR; + bool MustBeFirstR; + bool ValidR = canEmitConjunction(RHS, CanNegateR, MustBeFirstR, IsOR); + assert(ValidR && "Valid conjunction/disjunction tree"); + (void)ValidR; - // In case of an OR we need to negate our operands and the result. - // (A v B) <=> not(not(A) ^ not(B)) - bool NegateOpsAndResult = Opcode == ISD::OR; - // We can negate the results of all previous operations by inverting the - // predicate flags giving us a free negation for one side. The other side - // must be negatable by itself. - if (NegateOpsAndResult) { - // See which side we can negate. - bool CanNegateL; - bool isValidL = isConjunctionDisjunctionTree(LHS, CanNegateL); - assert(isValidL && "Valid conjunction/disjunction tree"); - (void)isValidL; + // Swap sub-tree that must come first to the right side. + if (MustBeFirstL) { + assert(!MustBeFirstR && "Valid conjunction/disjunction tree"); + std::swap(LHS, RHS); + std::swap(CanNegateL, CanNegateR); + std::swap(MustBeFirstL, MustBeFirstR); + } -#ifndef NDEBUG - bool CanNegateR; - bool isValidR = isConjunctionDisjunctionTree(RHS, CanNegateR); - assert(isValidR && "Valid conjunction/disjunction tree"); - assert((CanNegateL || CanNegateR) && "Valid conjunction/disjunction tree"); -#endif - - // Order the side which we cannot negate to RHS so we can emit it first. - if (!CanNegateL) + bool NegateR; + bool NegateAfterR; + bool NegateL; + bool NegateAfterAll; + if (Opcode == ISD::OR) { + // Swap the sub-tree that we can negate naturally to the left. + if (!CanNegateL) { + assert(CanNegateR && "at least one side must be negatable"); + assert(!MustBeFirstR && "invalid conjunction/disjunction tree"); + assert(!Negate); std::swap(LHS, RHS); + NegateR = false; + NegateAfterR = true; + } else { + // Negate the left sub-tree if possible, otherwise negate the result. + NegateR = CanNegateR; + NegateAfterR = !CanNegateR; + } + NegateL = true; + NegateAfterAll = !Negate; } else { - bool NeedsNegOutL = LHS->getOpcode() == ISD::OR; - assert((!NeedsNegOutL || RHS->getOpcode() != ISD::OR) && - "Valid conjunction/disjunction tree"); - // Order the side where we need to negate the output flags to RHS so it - // gets emitted first. - if (NeedsNegOutL) - std::swap(LHS, RHS); + assert(Opcode == ISD::AND && "Valid conjunction/disjunction tree"); + assert(!Negate && "Valid conjunction/disjunction tree"); + + NegateL = false; + NegateR = false; + NegateAfterR = false; + NegateAfterAll = false; } - // Emit RHS. If we want to negate the tree we only need to push a negate - // through if we are already in a PushNegate case, otherwise we can negate - // the "flags to test" afterwards. + // Emit sub-trees. AArch64CC::CondCode RHSCC; - SDValue CmpR = emitConjunctionDisjunctionTreeRec(DAG, RHS, RHSCC, Negate, - CCOp, Predicate); - if (NegateOpsAndResult && !Negate) + SDValue CmpR = emitConjunctionRec(DAG, RHS, RHSCC, NegateR, CCOp, Predicate); + if (NegateAfterR) RHSCC = AArch64CC::getInvertedCondCode(RHSCC); - // Emit LHS. We may need to negate it. - SDValue CmpL = emitConjunctionDisjunctionTreeRec(DAG, LHS, OutCC, - NegateOpsAndResult, CmpR, - RHSCC); - // If we transformed an OR to and AND then we have to negate the result - // (or absorb the Negate parameter). - if (NegateOpsAndResult && !Negate) + SDValue CmpL = emitConjunctionRec(DAG, LHS, OutCC, NegateL, CmpR, RHSCC); + if (NegateAfterAll) OutCC = AArch64CC::getInvertedCondCode(OutCC); return CmpL; } -/// Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain -/// of CCMP/CFCMP ops. See @ref AArch64CCMP. -/// \see emitConjunctionDisjunctionTreeRec(). -static SDValue emitConjunctionDisjunctionTree(SelectionDAG &DAG, SDValue Val, - AArch64CC::CondCode &OutCC) { - bool CanNegate; - if (!isConjunctionDisjunctionTree(Val, CanNegate)) +/// Emit expression as a conjunction (a series of CCMP/CFCMP ops). +/// In some cases this is even possible with OR operations in the expression. +/// See \ref AArch64CCMP. +/// \see emitConjunctionRec(). +static SDValue emitConjunction(SelectionDAG &DAG, SDValue Val, + AArch64CC::CondCode &OutCC) { + bool DummyCanNegate; + bool DummyMustBeFirst; + if (!canEmitConjunction(Val, DummyCanNegate, DummyMustBeFirst, false)) return SDValue(); - return emitConjunctionDisjunctionTreeRec(DAG, Val, OutCC, false, SDValue(), - AArch64CC::AL); + return emitConjunctionRec(DAG, Val, OutCC, false, SDValue(), AArch64CC::AL); } /// @} @@ -1859,7 +1891,7 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, } if (!Cmp && (RHSC->isNullValue() || RHSC->isOne())) { - if ((Cmp = emitConjunctionDisjunctionTree(DAG, LHS, AArch64CC))) { + if ((Cmp = emitConjunction(DAG, LHS, AArch64CC))) { if ((CC == ISD::SETNE) ^ RHSC->isNullValue()) AArch64CC = AArch64CC::getInvertedCondCode(AArch64CC); } Modified: projects/clang700-import/contrib/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp ============================================================================== --- projects/clang700-import/contrib/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp Sun Dec 9 11:36:04 2018 (r341763) @@ -90,7 +90,6 @@ class UnmangledFuncInfo { public: using ID = AMDGPULibFunc::EFuncId; - UnmangledFuncInfo() = default; UnmangledFuncInfo(StringRef _Name, unsigned _NumArgs) : Name(_Name), NumArgs(_NumArgs) {} // Get index to Table by function name. Modified: projects/clang700-import/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp ============================================================================== --- projects/clang700-import/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Sun Dec 9 11:36:04 2018 (r341763) @@ -25,6 +25,7 @@ #include "llvm/MC/MCFixupKindInfo.h" #include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCSymbolELF.h" #include "llvm/MC/MCTargetOptions.h" #include "llvm/MC/MCValue.h" #include "llvm/Support/ErrorHandling.h" @@ -566,6 +567,14 @@ bool MipsAsmBackend::shouldForceRelocation(const MCAss case Mips::fixup_MICROMIPS_TLS_TPREL_LO16: return true; } +} + +bool MipsAsmBackend::isMicroMips(const MCSymbol *Sym) const { + if (const auto *ElfSym = dyn_cast<const MCSymbolELF>(Sym)) { + if (ElfSym->getOther() & ELF::STO_MIPS_MICROMIPS) + return true; + } + return false; } MCAsmBackend *llvm::createMipsAsmBackend(const Target &T, Modified: projects/clang700-import/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h ============================================================================== --- projects/clang700-import/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h Sun Dec 9 11:36:04 2018 (r341763) @@ -25,6 +25,7 @@ class MCAssembler; struct MCFixupKindInfo; class MCObjectWriter; class MCRegisterInfo; +class MCSymbolELF; class Target; class MipsAsmBackend : public MCAsmBackend { @@ -90,6 +91,7 @@ class MipsAsmBackend : public MCAsmBackend { (public) bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) override; + bool isMicroMips(const MCSymbol *Sym) const override; }; // class MipsAsmBackend } // namespace Modified: projects/clang700-import/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp ============================================================================== --- projects/clang700-import/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp Sun Dec 9 11:36:04 2018 (r341763) @@ -15,6 +15,7 @@ #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCContext.h" +#include "llvm/MC/MCDwarf.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCSymbolELF.h" @@ -51,6 +52,22 @@ void MipsELFStreamer::EmitInstruction(const MCInst &In } createPendingLabelRelocs(); +} + +void MipsELFStreamer::EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) { + Frame.Begin = getContext().createTempSymbol(); + MCELFStreamer::EmitLabel(Frame.Begin); +} + +MCSymbol *MipsELFStreamer::EmitCFILabel() { + MCSymbol *Label = getContext().createTempSymbol("cfi", true); + MCELFStreamer::EmitLabel(Label); + return Label; +} + +void MipsELFStreamer::EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) { + Frame.End = getContext().createTempSymbol(); + MCELFStreamer::EmitLabel(Frame.End); } void MipsELFStreamer::createPendingLabelRelocs() { Modified: projects/clang700-import/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h ============================================================================== --- projects/clang700-import/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h Sun Dec 9 11:36:04 2018 (r341763) @@ -26,6 +26,7 @@ class MCAsmBackend; class MCCodeEmitter; class MCContext; class MCSubtargetInfo; +struct MCDwarfFrameInfo; class MipsELFStreamer : public MCELFStreamer { SmallVector<std::unique_ptr<MipsOptionRecord>, 8> MipsOptionRecords; @@ -59,6 +60,12 @@ class MipsELFStreamer : public MCELFStreamer { (public /// directives are emitted. void EmitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc) override; void EmitIntValue(uint64_t Value, unsigned Size) override; + + // Overriding these functions allows us to avoid recording of these labels + // in EmitLabel and later marking them as microMIPS. + void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override; + void EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override; + MCSymbol *EmitCFILabel() override; /// Emits all the option records stored up until the point it's called. void EmitMipsOptionRecords(); Modified: projects/clang700-import/contrib/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td ============================================================================== --- projects/clang700-import/contrib/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td Sun Dec 9 11:36:04 2018 (r341763) @@ -1733,7 +1733,7 @@ defm S_MMR6 : Cmp_Pats<f32, NOR_MMR6, ZERO>, ISA_MICRO defm D_MMR6 : Cmp_Pats<f64, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6; def : MipsPat<(f32 fpimm0), (MTC1_MMR6 ZERO)>, ISA_MICROMIPS32R6; -def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6 (MTC1 ZERO))>, ISA_MICROMIPS32R6; +def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6 (MTC1_MMR6 ZERO))>, ISA_MICROMIPS32R6; def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), (TRUNC_W_D_MMR6 FGR64Opnd:$src)>, ISA_MICROMIPS32R6; Modified: projects/clang700-import/contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td ============================================================================== --- projects/clang700-import/contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td Sun Dec 9 11:36:04 2018 (r341763) @@ -838,7 +838,7 @@ def : MipsPat<(i64 (sext (i32 (sub GPR32:$src, GPR32:$ (SUBu GPR32:$src, GPR32:$src2), sub_32)>; def : MipsPat<(i64 (sext (i32 (mul GPR32:$src, GPR32:$src2)))), (INSERT_SUBREG (i64 (IMPLICIT_DEF)), - (MUL GPR32:$src, GPR32:$src2), sub_32)>; + (MUL GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS3_NOT_32R6_64R6; def : MipsPat<(i64 (sext (i32 (MipsMFHI ACC64:$src)))), (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (PseudoMFHI ACC64:$src), sub_32)>; @@ -1139,3 +1139,6 @@ def SLTUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rs) "sltu\t$rs, $rt, $imm">, GPR_64; def : MipsInstAlias<"sltu\t$rs, $imm", (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm)>, GPR_64; + +def : MipsInstAlias<"rdhwr $rt, $rs", + (RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, GPR_64; Modified: projects/clang700-import/contrib/llvm/lib/Target/Mips/Mips64r6InstrInfo.td ============================================================================== --- projects/clang700-import/contrib/llvm/lib/Target/Mips/Mips64r6InstrInfo.td Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/Target/Mips/Mips64r6InstrInfo.td Sun Dec 9 11:36:04 2018 (r341763) @@ -301,6 +301,9 @@ def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i // Patterns used for matching away redundant sign extensions. // MIPS32 arithmetic instructions sign extend their result implicitly. +def : MipsPat<(i64 (sext (i32 (mul GPR32:$src, GPR32:$src2)))), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), + (MUL_R6 GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6; def : MipsPat<(i64 (sext (i32 (sdiv GPR32:$src, GPR32:$src2)))), (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (DIV GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6; Modified: projects/clang700-import/contrib/llvm/lib/Target/Mips/MipsFastISel.cpp ============================================================================== --- projects/clang700-import/contrib/llvm/lib/Target/Mips/MipsFastISel.cpp Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/Target/Mips/MipsFastISel.cpp Sun Dec 9 11:36:04 2018 (r341763) @@ -953,6 +953,11 @@ bool MipsFastISel::selectBranch(const Instruction *I) MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; // For now, just try the simplest case where it's fed by a compare. if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { + MVT CIMVT = + TLI.getValueType(DL, CI->getOperand(0)->getType(), true).getSimpleVT(); + if (CIMVT == MVT::i1) + return false; + unsigned CondReg = getRegForValue(CI); BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ)) .addReg(CondReg) Modified: projects/clang700-import/contrib/llvm/lib/Target/Mips/MipsInstrFPU.td ============================================================================== --- projects/clang700-import/contrib/llvm/lib/Target/Mips/MipsInstrFPU.td Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/Target/Mips/MipsInstrFPU.td Sun Dec 9 11:36:04 2018 (r341763) @@ -485,14 +485,14 @@ let AdditionalPredicates = [NotInMicroMips] in { def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>, ISA_MIPS1; - def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, - bitconvert>, MFC1_FM<0>, ISA_MIPS1; + def MFC1 : MMRel, StdMMR6Rel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, + bitconvert>, MFC1_FM<0>, ISA_MIPS1; def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>, ISA_MIPS1, FGR_64 { let DecoderNamespace = "MipsFP64"; } - def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, - bitconvert>, MFC1_FM<4>, ISA_MIPS1; + def MTC1 : MMRel, StdMMR6Rel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, + bitconvert>, MFC1_FM<4>, ISA_MIPS1; def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>, ISA_MIPS1, FGR_64 { let DecoderNamespace = "MipsFP64"; Modified: projects/clang700-import/contrib/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp ============================================================================== --- projects/clang700-import/contrib/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp Sun Dec 9 11:36:04 2018 (r341763) @@ -299,8 +299,12 @@ bool ExpandPseudo::expandBuildPairF64(MachineBasicBloc // register). Unfortunately, we have to make this decision before register // allocation so for now we use a spill/reload sequence for all // double-precision values in regardless of being an odd/even register. - if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) || - (FP64 && !Subtarget.useOddSPReg())) { + // + // For the cases that should be covered here MipsSEISelDAGToDAG adds $sp as + // implicit operand, so other passes (like ShrinkWrapping) are aware that + // stack is used. + if (I->getNumOperands() == 4 && I->getOperand(3).isReg() + && I->getOperand(3).getReg() == Mips::SP) { unsigned DstReg = I->getOperand(0).getReg(); unsigned LoReg = I->getOperand(1).getReg(); unsigned HiReg = I->getOperand(2).getReg(); @@ -360,9 +364,12 @@ bool ExpandPseudo::expandExtractElementF64(MachineBasi // register). Unfortunately, we have to make this decision before register // allocation so for now we use a spill/reload sequence for all // double-precision values in regardless of being an odd/even register. - - if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) || - (FP64 && !Subtarget.useOddSPReg())) { + // + // For the cases that should be covered here MipsSEISelDAGToDAG adds $sp as + // implicit operand, so other passes (like ShrinkWrapping) are aware that + // stack is used. + if (I->getNumOperands() == 4 && I->getOperand(3).isReg() + && I->getOperand(3).getReg() == Mips::SP) { unsigned DstReg = I->getOperand(0).getReg(); unsigned SrcReg = Op1.getReg(); unsigned N = Op2.getImm(); Modified: projects/clang700-import/contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp ============================================================================== --- projects/clang700-import/contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Sun Dec 9 11:36:04 2018 (r341763) @@ -238,6 +238,18 @@ void MipsSEDAGToDAGISel::processFunctionAfterISel(Mach case Mips::WRDSP: addDSPCtrlRegOperands(true, MI, MF); break; + case Mips::BuildPairF64_64: + case Mips::ExtractElementF64_64: + if (!Subtarget->useOddSPReg()) { + MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true)); + break; + } + // fallthrough + case Mips::BuildPairF64: + case Mips::ExtractElementF64: + if (Subtarget->isABI_FPXX() && !Subtarget->hasMTHC1()) + MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true)); + break; default: replaceUsesWithZeroReg(MRI, MI); } Modified: projects/clang700-import/contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp ============================================================================== --- projects/clang700-import/contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp Sun Dec 9 11:36:04 2018 (r341763) @@ -25,9 +25,14 @@ using namespace llvm; +static unsigned getUnconditionalBranch(const MipsSubtarget &STI) { + if (STI.inMicroMipsMode()) + return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM; + return STI.isPositionIndependent() ? Mips::B : Mips::J; +} + MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI) - : MipsInstrInfo(STI, STI.isPositionIndependent() ? Mips::B : Mips::J), - RI() {} + : MipsInstrInfo(STI, getUnconditionalBranch(STI)), RI() {} const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const { return RI; @@ -643,7 +648,7 @@ unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J || - Opc == Mips::B_MM || Opc == Mips::BEQZC_MM || + Opc == Mips::J_MM || Opc == Mips::B_MM || Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC || Opc == Mips::BLTC || Opc == Mips::BGEC || Opc == Mips::BLTUC || Opc == Mips::BGEUC || Opc == Mips::BGTZC || Opc == Mips::BLEZC || Modified: projects/clang700-import/contrib/llvm/lib/Target/PowerPC/P9InstrResources.td ============================================================================== --- projects/clang700-import/contrib/llvm/lib/Target/PowerPC/P9InstrResources.td Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/Target/PowerPC/P9InstrResources.td Sun Dec 9 11:36:04 2018 (r341763) @@ -592,6 +592,7 @@ def : InstRW<[P9_PM_3C, IP_EXECO_1C, IP_EXECE_1C, DISP XXPERM, XXPERMR, XXSLDWI, + XXSLDWIs, XXSPLTIB, XXSPLTW, XXSPLTWs, Modified: projects/clang700-import/contrib/llvm/lib/Target/PowerPC/PPCISelLowering.cpp ============================================================================== --- projects/clang700-import/contrib/llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sun Dec 9 11:36:04 2018 (r341763) @@ -8454,17 +8454,6 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue if (V2.isUndef() && PPC::isSplatShuffleMask(SVOp, 4)) { int SplatIdx = PPC::getVSPLTImmediate(SVOp, 4, DAG); - // If the source for the shuffle is a scalar_to_vector that came from a - // 32-bit load, it will have used LXVWSX so we don't need to splat again. - if (Subtarget.hasP9Vector() && - ((isLittleEndian && SplatIdx == 3) || - (!isLittleEndian && SplatIdx == 0))) { - SDValue Src = V1.getOperand(0); - if (Src.getOpcode() == ISD::SCALAR_TO_VECTOR && - Src.getOperand(0).getOpcode() == ISD::LOAD && - Src.getOperand(0).hasOneUse()) - return V1; - } SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1); SDValue Splat = DAG.getNode(PPCISD::XXSPLT, dl, MVT::v4i32, Conv, DAG.getConstant(SplatIdx, dl, MVT::i32)); Modified: projects/clang700-import/contrib/llvm/lib/Target/PowerPC/PPCInstrVSX.td ============================================================================== --- projects/clang700-import/contrib/llvm/lib/Target/PowerPC/PPCInstrVSX.td Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/Target/PowerPC/PPCInstrVSX.td Sun Dec 9 11:36:04 2018 (r341763) @@ -877,6 +877,12 @@ let Uses = [RM] in { "xxsldwi $XT, $XA, $XB, $SHW", IIC_VecPerm, [(set v4i32:$XT, (PPCvecshl v4i32:$XA, v4i32:$XB, imm32SExt16:$SHW))]>; + + let isCodeGenOnly = 1 in + def XXSLDWIs : XX3Form_2s<60, 2, + (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$SHW), + "xxsldwi $XT, $XA, $XA, $SHW", IIC_VecPerm, []>; + def XXSPLTW : XX2Form_2<60, 164, (outs vsrc:$XT), (ins vsrc:$XB, u2imm:$UIM), "xxspltw $XT, $XB, $UIM", IIC_VecPerm, @@ -886,6 +892,7 @@ let Uses = [RM] in { def XXSPLTWs : XX2Form_2<60, 164, (outs vsrc:$XT), (ins vfrc:$XB, u2imm:$UIM), "xxspltw $XT, $XB, $UIM", IIC_VecPerm, []>; + } // hasSideEffects } // UseVSXReg = 1 @@ -1466,8 +1473,6 @@ let AddedComplexity = 400 in { // Prefer VSX patterns (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S, 1)))))), (f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>; } - def : Pat<(v4i32 (scalar_to_vector ScalarLoads.Li32)), - (v4i32 (XXSPLTWs (LIWAX xoaddr:$src), 1))>; // Instructions for converting float to i64 feeding a store. let Predicates = [NoP9Vector] in { @@ -3050,14 +3055,48 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] (STXVX $rS, xoaddr:$dst)>; def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, xoaddr:$dst), (STXVX $rS, xoaddr:$dst)>; - def : Pat<(v4i32 (scalar_to_vector (i32 (load xoaddr:$src)))), - (v4i32 (LXVWSX xoaddr:$src))>; - def : Pat<(v4f32 (scalar_to_vector (f32 (load xoaddr:$src)))), - (v4f32 (LXVWSX xoaddr:$src))>; - def : Pat<(v4f32 (scalar_to_vector - (f32 (fpround (f64 (extloadf32 xoaddr:$src)))))), - (v4f32 (LXVWSX xoaddr:$src))>; + let AddedComplexity = 400 in { + // LIWAX - This instruction is used for sign extending i32 -> i64. + // LIWZX - This instruction will be emitted for i32, f32, and when + // zero-extending i32 to i64 (zext i32 -> i64). + let Predicates = [IsLittleEndian] in { + + def : Pat<(v2i64 (scalar_to_vector (i64 (sextloadi32 xoaddr:$src)))), + (v2i64 (XXPERMDIs + (COPY_TO_REGCLASS (LIWAX xoaddr:$src), VSRC), 2))>; + + def : Pat<(v2i64 (scalar_to_vector (i64 (zextloadi32 xoaddr:$src)))), + (v2i64 (XXPERMDIs + (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 2))>; + + def : Pat<(v4i32 (scalar_to_vector (i32 (load xoaddr:$src)))), + (v4i32 (XXPERMDIs + (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 2))>; + + def : Pat<(v4f32 (scalar_to_vector (f32 (load xoaddr:$src)))), + (v4f32 (XXPERMDIs + (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 2))>; + } + + let Predicates = [IsBigEndian] in { + def : Pat<(v2i64 (scalar_to_vector (i64 (sextloadi32 xoaddr:$src)))), + (v2i64 (COPY_TO_REGCLASS (LIWAX xoaddr:$src), VSRC))>; + + def : Pat<(v2i64 (scalar_to_vector (i64 (zextloadi32 xoaddr:$src)))), + (v2i64 (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC))>; + + def : Pat<(v4i32 (scalar_to_vector (i32 (load xoaddr:$src)))), + (v4i32 (XXSLDWIs + (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 1))>; + + def : Pat<(v4f32 (scalar_to_vector (f32 (load xoaddr:$src)))), + (v4f32 (XXSLDWIs + (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 1))>; + } + + } + // Build vectors from i8 loads def : Pat<(v16i8 (scalar_to_vector ScalarLoads.Li8)), (v16i8 (VSPLTBs 7, (LXSIBZX xoaddr:$src)))>; @@ -3218,6 +3257,39 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] def : Pat<(f32 (fpround (f64 (extloadf32 ixaddr:$src)))), (f32 (DFLOADf32 ixaddr:$src))>; + + let AddedComplexity = 400 in { + // The following pseudoinstructions are used to ensure the utilization + // of all 64 VSX registers. + let Predicates = [IsLittleEndian, HasP9Vector] in { + def : Pat<(v2i64 (scalar_to_vector (i64 (load ixaddr:$src)))), + (v2i64 (XXPERMDIs + (COPY_TO_REGCLASS (DFLOADf64 ixaddr:$src), VSRC), 2))>; + def : Pat<(v2i64 (scalar_to_vector (i64 (load xaddr:$src)))), + (v2i64 (XXPERMDIs + (COPY_TO_REGCLASS (XFLOADf64 xaddr:$src), VSRC), 2))>; + + def : Pat<(v2f64 (scalar_to_vector (f64 (load ixaddr:$src)))), + (v2f64 (XXPERMDIs + (COPY_TO_REGCLASS (DFLOADf64 ixaddr:$src), VSRC), 2))>; + def : Pat<(v2f64 (scalar_to_vector (f64 (load xaddr:$src)))), + (v2f64 (XXPERMDIs + (COPY_TO_REGCLASS (XFLOADf64 xaddr:$src), VSRC), 2))>; + } + + let Predicates = [IsBigEndian, HasP9Vector] in { + def : Pat<(v2i64 (scalar_to_vector (i64 (load ixaddr:$src)))), + (v2i64 (COPY_TO_REGCLASS (DFLOADf64 ixaddr:$src), VSRC))>; + def : Pat<(v2i64 (scalar_to_vector (i64 (load xaddr:$src)))), + (v2i64 (COPY_TO_REGCLASS (XFLOADf64 xaddr:$src), VSRC))>; + + def : Pat<(v2f64 (scalar_to_vector (f64 (load ixaddr:$src)))), + (v2f64 (COPY_TO_REGCLASS (DFLOADf64 ixaddr:$src), VSRC))>; + def : Pat<(v2f64 (scalar_to_vector (f64 (load xaddr:$src)))), + (v2f64 (COPY_TO_REGCLASS (XFLOADf64 xaddr:$src), VSRC))>; + } + } + let Predicates = [IsBigEndian, HasP9Vector] in { // (Un)Signed DWord vector extract -> QP @@ -3932,3 +4004,4 @@ let AddedComplexity = 400 in { (v4i32 (VEXTSH2W $A))>; } } + Modified: projects/clang700-import/contrib/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp ============================================================================== --- projects/clang700-import/contrib/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp Sun Dec 9 11:36:04 2018 (r341763) @@ -2924,12 +2924,20 @@ static Value *foldICmpWithLowBitMaskedVal(ICmpInst &I, // x & (-1 >> y) s>= x -> x s<= (-1 >> y) if (X != I.getOperand(1)) // X must be on RHS of comparison! return nullptr; // Ignore the other case. + if (!match(M, m_Constant())) // Can not do this fold with non-constant. + return nullptr; + if (!match(M, m_NonNegative())) // Must not have any -1 vector elements. + return nullptr; DstPred = ICmpInst::Predicate::ICMP_SLE; break; case ICmpInst::Predicate::ICMP_SLT: // x & (-1 >> y) s< x -> x s> (-1 >> y) if (X != I.getOperand(1)) // X must be on RHS of comparison! return nullptr; // Ignore the other case. + if (!match(M, m_Constant())) // Can not do this fold with non-constant. + return nullptr; + if (!match(M, m_NonNegative())) // Must not have any -1 vector elements. + return nullptr; DstPred = ICmpInst::Predicate::ICMP_SGT; break; case ICmpInst::Predicate::ICMP_SLE: Modified: projects/clang700-import/contrib/llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp ============================================================================== --- projects/clang700-import/contrib/llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp Sun Dec 9 11:36:04 2018 (r341763) @@ -231,17 +231,17 @@ struct TransformedFunction { TransformedFunction& operator=(TransformedFunction&&) = default; /// Type of the function before the transformation. - FunctionType* const OriginalType; + FunctionType *OriginalType; /// Type of the function after the transformation. - FunctionType* const TransformedType; + FunctionType *TransformedType; /// Transforming a function may change the position of arguments. This /// member records the mapping from each argument's old position to its new /// position. Argument positions are zero-indexed. If the transformation /// from F to F' made the first argument of F into the third argument of F', /// then ArgumentIndexMapping[0] will equal 2. - const std::vector<unsigned> ArgumentIndexMapping; + std::vector<unsigned> ArgumentIndexMapping; }; /// Given function attributes from a call site for the original function, Modified: projects/clang700-import/contrib/llvm/lib/Transforms/Utils/LCSSA.cpp ============================================================================== --- projects/clang700-import/contrib/llvm/lib/Transforms/Utils/LCSSA.cpp Sun Dec 9 06:52:25 2018 (r341762) +++ projects/clang700-import/contrib/llvm/lib/Transforms/Utils/LCSSA.cpp Sun Dec 9 11:36:04 2018 (r341763) @@ -41,6 +41,7 @@ #include "llvm/IR/Dominators.h" #include "llvm/IR/Function.h" #include "llvm/IR/Instructions.h" +#include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/PredIteratorCache.h" #include "llvm/Pass.h" #include "llvm/Transforms/Utils.h" *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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