Date: Thu, 27 Apr 2006 20:28:42 +0100 From: "Steven Hartland" <killing@multiplay.co.uk> To: <obrien@freebsd.org> Cc: Mike Jakubik <mikej@rogers.com>, freebsd-performance@freebsd.org, Bill Moran <wmoran@collaborativefusion.com>, David Gilbert <dgilbert@dclg.ca> Subject: Re: Dual-core CPU vs. very large cache Message-ID: <00b101c66a30$ceb32820$b3db87d4@multiplay.co.uk> References: <44503AC6.3060609@rogers.com> <007901c669eb$4a28d9a0$b3db87d4@multiplay.co.uk> <20060427190313.GB2741@dragon.NUXI.org>
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----- Original Message -----
From: "David O'Brien"
> On Thu, Apr 27, 2006 at 12:11:05PM +0100, Steven Hartland wrote:
>> Getting off topic now but I'd submit to you that a 1207 pin vs 940 pin
>> is setting up for the access requirements of quad core something that
>> AM2 is not going to be capable of hence quite different indeed.
>
> Nope. Quad core is internal connections between cores - not external.
> So you don't need extra pins to support quad-core vs. dual-core.
There was talk that there would be an enhanced memory controller
or possibly dual memory controllers in quad core cpus
which would be supported by the extra pins in Socket-F.
Either way I suspect that the additional pins will be used to
provide additional external bandwidth to successfully supply
the upcoming multi core CPU's with enough data so they aren't
starved.
All hearsay though as I've not see any real specs :)
Steve
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