Date: Thu, 31 Aug 1995 09:25:14 +0930 (CST) From: Michael Smith <msmith@atrad.adelaide.edu.au> To: rgrimes@gndrsh.aac.dev.com (Rodney W. Grimes) Cc: marino.ladavac@aut.alcatel.at, hardware@freebsd.org Subject: Re: Upgrade to my machine Message-ID: <199508302355.JAA29910@genesis.atrad.adelaide.edu.au> In-Reply-To: <199508301833.LAA08959@gndrsh.aac.dev.com> from "Rodney W. Grimes" at Aug 30, 95 11:33:14 am
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Rodney W. Grimes stands accused of saying: > > > THINK for a minute about large applications. An Intel Pentium 90/100 CPU > > > chip as 3.3 billon transistors on it. Each cmos transitor takes at least > > ^^^^^^ > > Minor nit. > > > > Million. Otherwise, we would have been having at least > > 500 megabyte RAM chips for several years now. Cheaply. > > > > I wish we did :) > > I will publically admit I may very well be in error here, 2 other folks > have sited references that state the number is 3.3 million, and I went > and checked 4 references here on this and they all say millon, but I am > really having a hard time fitting the Pentium design into 3.3 million > transistors from a few simple calculations. > > 16k of static sram takes >768K transistors assuming a 6 transistor cell, > now perhaps the cache is done in quasi-static 4 cell cmos sram, but then > how do they do stop clock ??? Perhaps the cache is invalidated when > coming out of stop clock mode, or maybe that is what happens during the > cycles it takes to shut down. Have a look at a die photo of one of those puppies, Rod. The cache occupies a _very_ substantial amount of real estate. (This is why on-chip caches are so small) > Also the claims that the RISC core of the 486 is in excess of a million > transistors in the 1994 data book sets makes me wonder how one could do > 2 of these for the dual issue super scaler pipe in anything less than > 2 million transistors. Because lots of the support logic is common. (clock generation, propagation etc.) > Perhaps the 3.3 million transistor count is the RISC super scaler core > excluding the cache, MMU, TLB and BIU _and_ microcode. No, that's the whole shebang. There's not much microcode, and you ought to know that shrapnel logic actually uses very few gates. > I don't directly consult for the processor group at Intel so I don't have > ready access to the right data. Published data like this is unclear as > to exactly what it is. >From some vendors at least 8) DEC are pretty clear that there are ~9M transistors on the biggest of the Alpha processors. Check out the die photos on the PowerPC homepage (off motorola's web site). The pictures for the 604 and 620 in particular offer good examples of how big the various bits are. > Anyway, the real point I was trying to make is there are things that > get _HUGE_ in the CAD applications with respect to memory needs. I You're spot on here. > Rod Grimes rgrimes@gndrsh.aac.dev.com -- ]] Mike Smith, Software Engineer msmith@atrad.adelaide.edu.au [[ ]] Genesis Software genesis@atrad.adelaide.edu.au [[ ]] High-speed data acquisition and [[ ]] realtime instrument control (ph/fax) +61-8-267-3039 [[ ]] My car has "demand start" -Terry Lambert UNIX: live FreeBSD or die! [[
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