Date: Thu, 02 Jul 1998 22:36:22 -0700 From: Mike Smith <mike@smith.net.au> To: "Jasmine(Yongqi) Wang" <jwang@cs.ubc.ca> Cc: freebsd-small@FreeBSD.ORG Subject: Re: (no subject) Message-ID: <199807030536.WAA04364@antipodes.cdrom.com> In-Reply-To: Your message of "Wed, 01 Jul 1998 13:55:12 PDT." <359AA230.A5D@cs.ubc.ca>
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> HI, there,
>
> I need to run some test to get an idea of TLB miss rate. I have found
> out that there is performance monitor counter in Pentium processors. I
> will run it on Pentium Pro.
>
> There are 4 MSRs, two for performance event select and two for counting.
> also there is RDMSR, WRMSR and RDPMC to use. so in my case the event
> type should be TLB miss and TLB hit.
>
> It's said the way it will work is to
> 1. set up PerfEvtSel0/1 with wrmsr
> 2. counter will start if 1 succeed and counter is enabled in above
> instruction.
>
> my questions are:
> RDMSR and WRMSR are only usable in Kernel mode, so should I make a small
> kernel or is there alternatives?
You haven't really been clear enough here. Are you trying to evaluate
TLB miss rates for a single process, or for the entire system? If for
just a single process, what do you plan to do to deal with the errors
introduced by interrupts and scheduling?
> when get the result back I can use RDPMC, if CR4[PCE]=1, i can get it in
> user mode; otherwise I can only run in kernel too. but i can't find any
> instruction to read CR4. There are instructions for CR0, CR2 and CR3, or
> I am missing sth. here?
It would be trivial to add a sysctl variable to obtain the value from
userland, should you wish to do so, as the handler runs in the kernel.
AFAIK, you can simply modify the support functions for the other CR
registers, eg. in sys/i386/i386/support.s:
/* rcr4() */
ENTRY(rcr4)
movl %cr4,%eax
ret
--
\\ Sometimes you're ahead, \\ Mike Smith
\\ sometimes you're behind. \\ mike@smith.net.au
\\ The race is long, and in the \\ msmith@freebsd.org
\\ end it's only with yourself. \\ msmith@cdrom.com
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