Date: Tue, 3 Aug 2010 00:26:18 +0000 (UTC) From: Nathan Whitehorn <nwhitehorn@FreeBSD.org> To: src-committers@freebsd.org, svn-src-user@freebsd.org Subject: svn commit: r210785 - in user/nwhitehorn/ps3/powerpc: aim include powerpc ps3 Message-ID: <201008030026.o730QInV081334@svn.freebsd.org>
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Author: nwhitehorn Date: Tue Aug 3 00:26:17 2010 New Revision: 210785 URL: http://svn.freebsd.org/changeset/base/210785 Log: Set up special registers on alternate Cell BE threads in a less hacky way, and tell the system about the features available on this CPU. SMP still works. Modified: user/nwhitehorn/ps3/powerpc/aim/mp_cpudep.c user/nwhitehorn/ps3/powerpc/include/spr.h user/nwhitehorn/ps3/powerpc/powerpc/cpu.c user/nwhitehorn/ps3/powerpc/ps3/platform_ps3.c Modified: user/nwhitehorn/ps3/powerpc/aim/mp_cpudep.c ============================================================================== --- user/nwhitehorn/ps3/powerpc/aim/mp_cpudep.c Mon Aug 2 23:57:50 2010 (r210784) +++ user/nwhitehorn/ps3/powerpc/aim/mp_cpudep.c Tue Aug 3 00:26:17 2010 (r210785) @@ -228,6 +228,21 @@ cpudep_save_config(void *dummy) powerpc_sync(); break; +#ifdef __powerpc64__ + case IBMCELLBE: + if (mfmsr() & PSL_HV) { + bsp_state[0] = mfspr(SPR_HID0); + bsp_state[1] = mfspr(SPR_HID1); + bsp_state[2] = mfspr(SPR_HID4); + bsp_state[3] = mfspr(SPR_HID6); + + bsp_state[4] = mfspr(SPR_CELL_TSCR); + } + + bsp_state[5] = mfspr(SPR_CELL_TSRL); + + break; +#endif case MPC7450: case MPC7455: case MPC7457: @@ -288,6 +303,21 @@ cpudep_ap_setup() powerpc_sync(); break; +#ifdef __powerpc64__ + case IBMCELLBE: + if (mfmsr() & PSL_HV) { + mtspr(SPR_HID0, bsp_state[0]); + mtspr(SPR_HID1, bsp_state[1]); + mtspr(SPR_HID4, bsp_state[2]); + mtspr(SPR_HID6, bsp_state[3]); + + mtspr(SPR_CELL_TSCR, bsp_state[4]); + } + + mtspr(SPR_CELL_TSRL, bsp_state[5]); + + break; +#endif case MPC7450: case MPC7455: case MPC7457: Modified: user/nwhitehorn/ps3/powerpc/include/spr.h ============================================================================== --- user/nwhitehorn/ps3/powerpc/include/spr.h Mon Aug 2 23:57:50 2010 (r210784) +++ user/nwhitehorn/ps3/powerpc/include/spr.h Tue Aug 3 00:26:17 2010 (r210785) @@ -420,6 +420,10 @@ #define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */ #define SPR_HID4 0x3f4 /* ..8 Hardware Implementation Register 4 */ #define SPR_HID5 0x3f6 /* ..8 Hardware Implementation Register 5 */ +#define SPR_HID6 0x3f9 /* ..8 Hardware Implementation Register 6 */ + +#define SPR_CELL_TSRL 0x380 /* ... Cell BE Thread Status Register */ +#define SPR_CELL_TSCR 0x399 /* ... Cell BE Thread Status Register */ #if defined(AIM) #define SPR_DBSR 0x3f0 /* 4.. Debug Status Register */ Modified: user/nwhitehorn/ps3/powerpc/powerpc/cpu.c ============================================================================== --- user/nwhitehorn/ps3/powerpc/powerpc/cpu.c Mon Aug 2 23:57:50 2010 (r210784) +++ user/nwhitehorn/ps3/powerpc/powerpc/cpu.c Tue Aug 3 00:26:17 2010 (r210785) @@ -145,6 +145,9 @@ static const struct cputab models[] = { 0, cpu_e500_setup }, { "Freescale e500v2 core", FSL_E500v2, REVFMT_MAJMIN, 0, cpu_e500_setup }, + { "IBM Cell Broadband Engine", IBMCELLBE, REVFMT_MAJMIN, + PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, + NULL}, { "Unknown PowerPC CPU", 0, REVFMT_HEX, 0, NULL }, }; Modified: user/nwhitehorn/ps3/powerpc/ps3/platform_ps3.c ============================================================================== --- user/nwhitehorn/ps3/powerpc/ps3/platform_ps3.c Mon Aug 2 23:57:50 2010 (r210784) +++ user/nwhitehorn/ps3/powerpc/ps3/platform_ps3.c Tue Aug 3 00:26:17 2010 (r210785) @@ -199,12 +199,6 @@ ps3_smp_start_cpu(platform_t plat, struc if (pc->pc_hwref != 1) return (ENXIO); - /* - * XXX: Set local thread priority to low, to match remote. - * XXX: Replace magic numbers with constants. - */ - mtspr(896, (mfspr(896) & 0xffffffff) | (0x1UL << 51)); - ap_pcpu = pc; *secondary_spin_sem = 1; powerpc_sync();
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