Date: Mon, 21 Nov 2011 12:03:03 -0700 From: Peter Grehan <grehan@freebsd.org> To: Nathan Whitehorn <nwhitehorn@freebsd.org> Cc: svn-src-projects@freebsd.org, src-committers@freebsd.org, bv <deboomerang@gmail.com> Subject: Re: svn commit: r227772 - in projects/pseries: amd64/amd64 amd64/conf amd64/ia32 amd64/include amd64/linux32 arm/arm arm/at91 arm/conf arm/econa arm/include arm/mv arm/sa11x0 arm/xscale/i80321 arm/xsca... Message-ID: <4ECAA067.7060906@freebsd.org> In-Reply-To: <4EC9D65C.6050106@freebsd.org> References: <201111202147.pAKLlR0i010700@svn.freebsd.org> <4EC98E99.9000601@freebsd.org> <4EC9D65C.6050106@freebsd.org>
next in thread | previous in thread | raw e-mail | index | archive | help
Hi Nathan, (cc'ing Bryan, virtio author) >> One thing to look out for is that the virtio spec has PCI register >> access in host-order, so you may need to switch in big-endian bus ops. ... > Is it worth making some generic way to avoid regular bus accessors? It > also needs to avoid regular bus dma calls, since the spec indicates > finger-of-God accesses that bypass any emulated IOMMU that busdma would > ordinarily try to use. The PCI interface for virtio specifies i/o space for device register access - that still needs bus space on x86 to get the right instructions issued. But, there's also a recent proposal to have additional BARs accessed via MMIO and not i/o. At least on x86 this still fits in fine with the standard PCI driver model. Is the p-series i/f a memory-mapped local-bus style of access, or is it via a pseudo PCI bus ? later, Peter.
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?4ECAA067.7060906>