Date: Thu, 4 Feb 2016 14:02:42 +0000 (UTC) From: Michal Meloun <mmel@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r295256 - head/sys/arm/arm Message-ID: <201602041402.u14E2gmV094518@repo.freebsd.org>
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Author: mmel Date: Thu Feb 4 14:02:42 2016 New Revision: 295256 URL: https://svnweb.freebsd.org/changeset/base/295256 Log: ARM: Set UNAL_ENABLE bit in SCTLR CP15 register. This bit is RAO/SBOP for ARMv7. For ARMv6, it controls ARMv5 compatible alignment support. This bit have no effect until unaligned access is enabled. Modified: head/sys/arm/arm/locore-v6.S Modified: head/sys/arm/arm/locore-v6.S ============================================================================== --- head/sys/arm/arm/locore-v6.S Thu Feb 4 13:35:40 2016 (r295255) +++ head/sys/arm/arm/locore-v6.S Thu Feb 4 14:02:42 2016 (r295256) @@ -132,9 +132,9 @@ ASENTRY_NP(_start) bic r7, #CPU_CONTROL_DC_ENABLE bic r7, #CPU_CONTROL_MMU_ENABLE bic r7, #CPU_CONTROL_IC_ENABLE - bic r7, #CPU_CONTROL_UNAL_ENABLE bic r7, #CPU_CONTROL_BPRD_ENABLE bic r7, #CPU_CONTROL_SW_ENABLE + orr r7, #CPU_CONTROL_UNAL_ENABLE orr r7, #CPU_CONTROL_AFLT_ENABLE orr r7, #CPU_CONTROL_VECRELOC mcr CP15_SCTLR(r7) @@ -456,9 +456,9 @@ ASENTRY_NP(mpentry) bic r0, #CPU_CONTROL_MMU_ENABLE bic r0, #CPU_CONTROL_DC_ENABLE bic r0, #CPU_CONTROL_IC_ENABLE - bic r0, #CPU_CONTROL_UNAL_ENABLE bic r0, #CPU_CONTROL_BPRD_ENABLE bic r0, #CPU_CONTROL_SW_ENABLE + orr r0, #CPU_CONTROL_UNAL_ENABLE orr r0, #CPU_CONTROL_AFLT_ENABLE orr r0, #CPU_CONTROL_VECRELOC mcr CP15_SCTLR(r0)
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