Date: Sat, 22 Nov 2008 13:26:26 -0800 From: kmacy@freebsd.org To: "Kostik Belousov" <kostikbel@gmail.com> Cc: svn-src-head@freebsd.org, svn-src-all@freebsd.org, src-committers@freebsd.org Subject: Re: svn commit: r185162 - in head: . sys/amd64/include sys/arm/include sys/conf sys/dev/bce sys/dev/cxgb sys/dev/cxgb/sys sys/dev/cxgb/ulp/iw_cxgb sys/dev/mxge sys/dev/nxge sys/i386/include sys/i386/in... Message-ID: <3c1674c90811221326m41e229f7p6abbc0eb473e900e@mail.gmail.com> In-Reply-To: <20081122112949.GA6408@deviant.kiev.zoral.com.ua> References: <200811220555.mAM5tuIJ007781@svn.freebsd.org> <20081122112949.GA6408@deviant.kiev.zoral.com.ua>
next in thread | previous in thread | raw e-mail | index | archive | help
This was a concern of mine - note that many driver writers assume they exist. Thoughts on efficiently handling it via checking cpuid at runtime? Alternatively we could have it be conditional on CPU_i786. On 11/22/08, Kostik Belousov <kostikbel@gmail.com> wrote: > On Sat, Nov 22, 2008 at 05:55:56AM +0000, Kip Macy wrote: >> Author: kmacy >> Date: Sat Nov 22 05:55:56 2008 >> New Revision: 185162 >> URL: http://svn.freebsd.org/changeset/base/185162 >> >> Log: >> - bump __FreeBSD version to reflect added buf_ring, memory barriers, >> and ifnet functions >> >> - add memory barriers to <machine/atomic.h> > >> Modified: head/sys/i386/include/atomic.h >> ============================================================================== >> --- head/sys/i386/include/atomic.h Sat Nov 22 01:48:20 2008 (r185161) >> +++ head/sys/i386/include/atomic.h Sat Nov 22 05:55:56 2008 (r185162) >> @@ -32,6 +32,21 @@ >> #error this file needs sys/cdefs.h as a prerequisite >> #endif >> >> + >> +#if defined(I686_CPU) >> +#define mb() __asm__ __volatile__ ("mfence;": : :"memory") >> +#define wmb() __asm__ __volatile__ ("sfence;": : :"memory") >> +#define rmb() __asm__ __volatile__ ("lfence;": : :"memory") >> +#else >> +/* >> + * do we need a serializing instruction? >> + */ >> +#define mb() >> +#define wmb() >> +#define rmb() >> +#endif >> + >> + >> /* >> * Various simple operations on memory, each of which is atomic in the >> * presence of interrupts and multiple processors. > AFAIR, sfence instruction was added with the Pentium III processor (SSE), > while lfence was introduced with the Pentium 4 (SSE2). > > I think that #ifdef I686_CPU handling of the fences is wrong. We need to > use a serialized instruction on CPUs that does not support corresponding > fence, if needed. > -- If we desire respect for the law, we must first make the law respectable. - Louis D. Brandeis
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?3c1674c90811221326m41e229f7p6abbc0eb473e900e>