Date: Tue, 27 Apr 2010 19:45:46 GMT From: Alexander Motin <mav@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 177412 for review Message-ID: <201004271945.o3RJjkIF067483@repoman.freebsd.org>
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http://p4web.freebsd.org/@@177412?ac=10 Change 177412 by mav@mav_mavtest on 2010/04/27 19:45:40 Cleanup and comment code. Affected files ... .. //depot/projects/scottl-camlock/src/sys/dev/mvs/mvs.c#16 edit .. //depot/projects/scottl-camlock/src/sys/dev/mvs/mvs.h#11 edit .. //depot/projects/scottl-camlock/src/sys/dev/mvs/mvs_if.m#2 edit .. //depot/projects/scottl-camlock/src/sys/dev/mvs/mvs_pci.c#5 edit .. //depot/projects/scottl-camlock/src/sys/dev/mvs/mvs_soc.c#5 edit Differences ... ==== //depot/projects/scottl-camlock/src/sys/dev/mvs/mvs.c#16 (text+ko) ==== @@ -25,7 +25,7 @@ */ #include <sys/cdefs.h> -__FBSDID("$FreeBSD: src/sys/dev/mvs/mvs.c,v 1.30 2010/03/21 18:18:58 mav Exp $"); +__FBSDID("$FreeBSD$"); #include <sys/param.h> #include <sys/module.h> @@ -401,11 +401,13 @@ struct mvs_channel *ch = device_get_softc(dev); uint64_t work; + /* Requests queue. */ work = ch->dma.workrq_bus; ATA_OUTL(ch->r_mem, EDMA_REQQBAH, work >> 32); ATA_OUTL(ch->r_mem, EDMA_REQQIP, work & 0xffffffff); ATA_OUTL(ch->r_mem, EDMA_REQQOP, work & 0xffffffff); bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, BUS_DMASYNC_PREWRITE); + /* Reponses queue. */ bzero(ch->dma.workrp, 256); work = ch->dma.workrp_bus; ATA_OUTL(ch->r_mem, EDMA_RESQBAH, work >> 32); @@ -440,8 +442,8 @@ ch->curr_mode = mode; ch->fbs_enabled = 0; ch->fake_busy = 0; + /* Report mode to controller. Needed for correct CCC operation. */ MVS_EDMA(device_get_parent(dev), dev, mode); -// device_printf(dev, "EDMA mode: %d\n", mode); /* Configure new mode. */ ecfg = EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2 | EDMA_CFG_EHOSTQUEUECACHEEN; if (ch->pm_present) { @@ -465,8 +467,8 @@ ecfg |= EDMA_CFG_ESATANATVCMDQUE; ATA_OUTL(ch->r_mem, EDMA_CFG, ecfg); mvs_setup_edma_queues(dev); - /* Configure FBS */ if (ch->quirks & MVS_Q_GENIIE) { + /* Configure FBS-related registers */ fcfg = ATA_INL(ch->r_mem, SATA_FISC); ltm = ATA_INL(ch->r_mem, SATA_LTM); hc = ATA_INL(ch->r_mem, EDMA_HC); @@ -498,10 +500,6 @@ unkn &= ~1; ATA_OUTL(ch->r_mem, EDMA_UNKN_RESD, unkn); } -// device_printf(dev, "fisc %08x\n",ATA_INL(ch->r_mem, SATA_FISC)); -// device_printf(dev, "ltmode %08x\n",ATA_INL(ch->r_mem, SATA_LTM)); -// device_printf(dev, "edmacfg %08x\n",ATA_INL(ch->r_mem, EDMA_CFG)); -// device_printf(dev, "haltcond %08x\n",ATA_INL(ch->r_mem, EDMA_HC)); /* Run EDMA. */ if (mode != MVS_EDMA_OFF) ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EENEDMA); @@ -535,9 +533,9 @@ union ccb *ccb; if (bootverbose) { - if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && - ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && - ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) { + if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) && + ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) && + ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE)) { device_printf(dev, "CONNECT requested\n"); } else device_printf(dev, "DISCONNECT requested\n"); @@ -563,6 +561,7 @@ uint32_t fis; int d; + /* Try to read PMP field from SDB FIS. Present only for Gen-IIe. */ fis = ATA_INL(ch->r_mem, SATA_FISDW0); if ((fis & 0x80ff) == 0x80a1) d = (fis & 0x0f00) >> 8; @@ -598,12 +597,13 @@ if (ch->numrslots != 0) return; + /* If we are idle - request power state transition. */ work = ATA_INL(ch->r_mem, SATA_SC); - work &= ~ATA_SC_SPM_MASK; + work &= ~SATA_SC_SPM_MASK; if (ch->pm_level == 4) - work |= ATA_SC_SPM_PARTIAL; + work |= SATA_SC_SPM_PARTIAL; else - work |= ATA_SC_SPM_SLUMBER; + work |= SATA_SC_SPM_SLUMBER; ATA_OUTL(ch->r_mem, SATA_SC, work); } @@ -614,11 +614,12 @@ uint32_t work; work = ATA_INL(ch->r_mem, SATA_SS); - if (work & ATA_SS_IPM_ACTIVE) + if (work & SATA_SS_IPM_ACTIVE) return; + /* If we are not in active state - request power state transition. */ work = ATA_INL(ch->r_mem, SATA_SC); - work &= ~ATA_SC_SPM_MASK; - work |= ATA_SC_SPM_ACTIVE; + work &= ~SATA_SC_SPM_MASK; + work |= SATA_SC_SPM_ACTIVE; ATA_OUTL(ch->r_mem, SATA_SC, work); } @@ -635,27 +636,33 @@ //device_printf(dev, "irq cause %02x EDMA %d IEC %08x\n", // arg->cause, edma, ATA_INL(ch->r_mem, EDMA_IEC)); + /* New item in response queue. */ if ((arg->cause & 2) && edma) mvs_crbq_intr(dev); + /* Some error or special event. */ if (arg->cause & 1) { iec = ATA_INL(ch->r_mem, EDMA_IEC); -device_printf(dev, "irq cause %02x EDMA %d IEC %08x\n", - arg->cause, edma, iec); +//device_printf(dev, "irq cause %02x EDMA %d IEC %08x\n", +// arg->cause, edma, iec); if (iec & EDMA_IE_SERRINT) { serr = ATA_INL(ch->r_mem, SATA_SE); ATA_OUTL(ch->r_mem, SATA_SE, serr); -device_printf(dev, "SERR %08x\n", serr); +//device_printf(dev, "SERR %08x\n", serr); } + /* EDMA self-disabled due to error. */ if (iec & EDMA_IE_ESELFDIS) selfdis = 1; + /* Transport interrupt. */ if (iec & EDMA_IE_ETRANSINT) { + /* For Gen-I this bit means self-disable. */ if (ch->quirks & MVS_Q_GENI) selfdis = 1; + /* For Gen-II this bit means SDB-N. */ else if (ch->quirks & MVS_Q_GENII) fisic = SATA_FISC_FISWAIT4HOSTRDYEN_B1; - else + else /* For Gen-IIe - read FIS interrupt cause. */ fisic = ATA_INL(ch->r_mem, SATA_FISIC); -device_printf(dev, "FISIC %08x\n", fisic); +//device_printf(dev, "FISIC %08x\n", fisic); } if (selfdis) ch->curr_mode = MVS_EDMA_UNKNOWN; @@ -729,14 +736,17 @@ mvs_end_transaction(&ch->slot[i], et); } } + /* Process SDB-N. */ if (fisic & SATA_FISC_FISWAIT4HOSTRDYEN_B1) mvs_notify_events(dev); if (fisic) ATA_OUTL(ch->r_mem, SATA_FISIC, ~fisic); + /* Process hot-plug. */ if ((iec & (EDMA_IE_EDEVDIS | EDMA_IE_EDEVCON)) || - (serr & ATA_SE_PHY_CHANGED)) + (serr & SATA_SE_PHY_CHANGED)) mvs_phy_check_events(dev, serr); } + /* Legacy mode device interrupt. */ if ((arg->cause & 2) && !edma) mvs_legacy_intr(dev); } @@ -767,7 +777,7 @@ u_int length; uint8_t status, ireason; - /* clear interrupt and get status */ + /* Clear interrupt and get status. */ status = mvs_getstatus(dev, 1); // device_printf(dev, "Legacy intr status %02x\n", // status); @@ -783,16 +793,16 @@ return; } } - /* if we got an error we are done with the HW */ + /* If we got an error, we are done. */ if (status & ATA_S_ERROR) { et = MVS_ERR_TFE; goto end_finished; } - if (ccb->ccb_h.func_code == XPT_ATA_IO) { + if (ccb->ccb_h.func_code == XPT_ATA_IO) { /* ATA PIO */ ccb->ataio.res.status = status; - /* are we moving data ? */ + /* Are we moving data? */ if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { - /* if read data get it */ + /* If data read command - get them. */ if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { device_printf(dev, "timeout waiting for read DRQ\n"); @@ -803,14 +813,14 @@ (uint16_t *)(ccb->ataio.data_ptr + ch->donecount), ch->transfersize / 2); } - /* update how far we've gotten */ + /* Update how far we've gotten. */ ch->donecount += ch->transfersize; - /* do we need a scoop more ? */ + /* Do we need more? */ if (ccb->ataio.dxfer_len > ch->donecount) { - /* set this transfer size according to HW capabilities */ + /* Set this transfer size according to HW capabilities */ ch->transfersize = min(ccb->ataio.dxfer_len - ch->donecount, ch->curr[ccb->ccb_h.target_id].bytecount); - /* if data write command, output the data */ + /* If data write command - put them */ if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { device_printf(dev, "timeout waiting for write DRQ\n"); @@ -822,7 +832,7 @@ ch->transfersize / 2); return; } - /* if data read command, return & wait for interrupt */ + /* If data read command, return & wait for interrupt */ if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) return; } @@ -832,6 +842,7 @@ et = MVS_ERR_TFE; else if (ATA_INL(ch->r_mem, DMA_S) & DMA_S_ERR) et = MVS_ERR_TFE; + /* Stop basic DMA. */ ATA_OUTL(ch->r_mem, DMA_C, 0); goto end_finished; } else { /* ATAPI PIO */ @@ -843,7 +854,7 @@ case ATAPI_P_CMDOUT: device_printf(dev, "ATAPI CMDOUT\n"); - /* return wait for interrupt */ + /* Return wait for interrupt */ return; case ATAPI_P_WRITE: @@ -858,10 +869,10 @@ (uint16_t *)(ccb->csio.data_ptr + ch->donecount), length / 2); ch->donecount += length; - /* set next transfer size according to HW capabilities */ + /* Set next transfer size according to HW capabilities */ ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount, ch->curr[ccb->ccb_h.target_id].bytecount); - /* return wait for interrupt */ + /* Return wait for interrupt */ return; case ATAPI_P_READ: @@ -875,10 +886,10 @@ (uint16_t *)(ccb->csio.data_ptr + ch->donecount), length / 2); ch->donecount += length; - /* set next transfer size according to HW capabilities */ + /* Set next transfer size according to HW capabilities */ ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount, ch->curr[ccb->ccb_h.target_id].bytecount); - /* return wait for interrupt */ + /* Return wait for interrupt */ return; case ATAPI_P_DONEDRQ: @@ -941,7 +952,7 @@ flags = le16toh(crpb->rspflg); //device_printf(dev, "CRPB %d %d %04x\n", cin_idx, slot, flags); /* - * Handle only successfull completions. + * Handle only successfull completions here. * Errors will be handled by main intr handler. */ if (ch->numtslots != 0 || (flags & EDMA_IE_EDEVERR) == 0) { @@ -1121,6 +1132,7 @@ uint8_t *cdb = (ccb->ccb_h.flags & CAM_CDB_POINTER) ? ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes; ch->numpslots++; + /* Use ATAPI DMA only for commands without under-/overruns. */ if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA && (cdb[0] == 0x08 || @@ -1212,7 +1224,7 @@ // device_printf(dev, "%d Legacy command %02x size %d\n", // port, ccb->ataio.cmd.command, ccb->ataio.dxfer_len); mvs_tfd_write(dev, ccb); - /* device reset doesn't interrupt */ + /* Device reset doesn't interrupt. */ if (ccb->ataio.cmd.command == ATA_DEVICE_RESET) { int timeout = 1000000; do { @@ -1227,7 +1239,7 @@ ch->curr[port].bytecount); if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) ch->fake_busy = 1; - /* if write command output the data */ + /* If data write command - output the data */ if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { device_printf(dev, "timeout waiting for write DRQ\n"); @@ -1245,6 +1257,7 @@ ch->donecount = 0; ch->transfersize = min(ccb->csio.dxfer_len, ch->curr[port].bytecount); + /* Write ATA PACKET command. */ if (ch->basic_dma) { ATA_OUTB(ch->r_mem, ATA_FEATURE, ATA_F_DMA); ATA_OUTB(ch->r_mem, ATA_CYL_LSB, 0); @@ -1256,7 +1269,7 @@ } ATA_OUTB(ch->r_mem, ATA_COMMAND, ATA_PACKET_CMD); ch->fake_busy = 1; - /* wait for ready to write ATAPI command block */ + /* Wait for ready to write ATAPI command block */ if (mvs_wait(dev, 0, ATA_S_BUSY, 1000) < 0) { device_printf(dev, "timeout waiting for ATAPI !BUSY\n"); mvs_end_transaction(slot, MVS_ERR_TIMEOUT); @@ -1277,12 +1290,14 @@ mvs_end_transaction(slot, MVS_ERR_TIMEOUT); return; } + /* Write ATAPI command. */ ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, (uint16_t *)((ccb->ccb_h.flags & CAM_CDB_POINTER) ? ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes), ch->curr[port].atapi / 2); DELAY(10); if (ch->basic_dma) { + /* Start basic DMA. */ eprd = ch->dma.workrq_bus + MVS_EPRD_OFFSET + (MVS_EPRD_SIZE * slot->slot); ATA_OUTL(ch->r_mem, DMA_DTLBA, eprd); @@ -1465,10 +1480,12 @@ if (slot->state < MVS_SLOT_RUNNING) return; device_printf(dev, "Timeout on slot %d\n", slot->slot); - device_printf(dev, "ic %08x iec %08x edma_s %08x dma_c %08x dma_s %08x rs %08x tfd %02x serr %08x\n", - ATA_INL(ch->r_mem, HC_IC), ATA_INL(ch->r_mem, EDMA_IEC), - ATA_INL(ch->r_mem, EDMA_S), ATA_INL(ch->r_mem, DMA_C), ATA_INL(ch->r_mem, DMA_S), ch->rslots, - ATA_INB(ch->r_mem, ATA_ALTSTAT), ATA_INL(ch->r_mem, SATA_SE)); + device_printf(dev, "iec %08x serr %08x edma_s %08x " + "dma_c %08x dma_s %08x rs %08x status %02x\n", + ATA_INL(ch->r_mem, EDMA_IEC), ATA_INL(ch->r_mem, SATA_SE), + ATA_INL(ch->r_mem, EDMA_S), ATA_INL(ch->r_mem, DMA_C), + ATA_INL(ch->r_mem, DMA_S), ch->rslots, + ATA_INB(ch->r_mem, ATA_ALTSTAT)); /* Handle frozen command. */ mvs_requeue_frozen(dev); /* We wait for other commands timeout and pray. */ @@ -1754,7 +1771,6 @@ return (-1); } } -// device_printf(dev, "Wait status %02x\n", st); return (timeout); } @@ -1872,11 +1888,11 @@ /* Wait up to 100ms for "connect well" */ for (timeout = 0; timeout < 100 ; timeout++) { status = ATA_INL(ch->r_mem, SATA_SS); - if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && - ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && - ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) + if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) && + ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) && + ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE)) break; - if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { + if ((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_OFFLINE) { if (bootverbose) { device_printf(ch->dev, "SATA offline status=%08x\n", status); @@ -1910,24 +1926,24 @@ sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; if (sata_rev == 1) - val = ATA_SC_SPD_SPEED_GEN1; + val = SATA_SC_SPD_SPEED_GEN1; else if (sata_rev == 2) - val = ATA_SC_SPD_SPEED_GEN2; + val = SATA_SC_SPD_SPEED_GEN2; else if (sata_rev == 3) - val = ATA_SC_SPD_SPEED_GEN3; + val = SATA_SC_SPD_SPEED_GEN3; else val = 0; ATA_OUTL(ch->r_mem, SATA_SC, - ATA_SC_DET_RESET | val | - ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); + SATA_SC_DET_RESET | val | + SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER); DELAY(5000); ATA_OUTL(ch->r_mem, SATA_SC, - ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : - (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); + SATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : + (SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER))); DELAY(5000); if (!mvs_sata_connect(ch)) { if (ch->pm_level > 0) - ATA_OUTL(ch->r_mem, SATA_SC, ATA_SC_DET_DISABLE); + ATA_OUTL(ch->r_mem, SATA_SC, SATA_SC_DET_DISABLE); return (0); } return (1); @@ -2019,7 +2035,7 @@ if (cts->type == CTS_TYPE_CURRENT_SETTINGS && (ccb->ccb_h.target_id == 15 || (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { - status = ATA_INL(ch->r_mem, SATA_SS) & ATA_SS_SPD_MASK; + status = ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_SPD_MASK; if (status & 0x0f0) { cts->xport_specific.sata.revision = (status & 0x0f0) >> 4; @@ -2079,7 +2095,7 @@ cpi->bus_id = cam_sim_bus(sim); cpi->base_transfer_speed = 150000; strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); - strncpy(cpi->hba_vid, "MVS", HBA_IDLEN); + strncpy(cpi->hba_vid, "Marvell", HBA_IDLEN); strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); cpi->unit_number = cam_sim_unit(sim); cpi->transport = XPORT_SATA; ==== //depot/projects/scottl-camlock/src/sys/dev/mvs/mvs.h#11 (text+ko) ==== @@ -23,7 +23,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * $FreeBSD: src/sys/dev/mvs/mvs.h,v 1.11 2010/02/14 12:30:35 mav Exp $ + * $FreeBSD$ */ #include "mvs_if.h" @@ -61,6 +61,7 @@ #define CHIP_SOC_LED 0x2C /* SoC LED Configuration */ +/* Chip CCC registers */ #define CHIP_ICC 0x18008 #define CHIP_ICC_ALL_PORTS (1 << 4) /* all ports irq event */ #define CHIP_ICT 0x180cc @@ -123,23 +124,24 @@ #define EDMA_IE_ESELFDIS (1 << 7) /* EDMA Self Disable */ #define EDMA_IE_ETRANSINT (1 << 8) /* Transport Layer */ #define EDMA_IE_EIORDYERR (1 << 12) /* EDMA IORdy Error */ -# define EDMA_IE_LINKXERR_SATACRC (1 << 0) /* SATA CRC error */ -# define EDMA_IE_LINKXERR_INTERNALFIFO (1 << 1) /* internal FIFO err */ -# define EDMA_IE_LINKXERR_LINKLAYERRESET (1 << 2) +#define EDMA_IE_LINKXERR_SATACRC (1 << 0) /* SATA CRC error */ +#define EDMA_IE_LINKXERR_INTERNALFIFO (1 << 1) /* internal FIFO err */ +#define EDMA_IE_LINKXERR_LINKLAYERRESET (1 << 2) /* Link Layer is reset by the reception of SYNC primitive from device */ -# define EDMA_IE_LINKXERR_OTHERERRORS (1 << 3) +#define EDMA_IE_LINKXERR_OTHERERRORS (1 << 3) /* * Link state errors, coding errors, or running disparity errors occur * during FIS reception. */ -# define EDMA_IE_LINKTXERR_FISTXABORTED (1 << 4) /* FIS Tx is aborted */ +#define EDMA_IE_LINKTXERR_FISTXABORTED (1 << 4) /* FIS Tx is aborted */ #define EDMA_IE_LINKCTLRXERR(x) ((x) << 13) /* Link Ctrl Recv Err */ #define EDMA_IE_LINKDATARXERR(x) ((x) << 17) /* Link Data Recv Err */ #define EDMA_IE_LINKCTLTXERR(x) ((x) << 21) /* Link Ctrl Tx Error */ #define EDMA_IE_LINKDATATXERR(x) ((x) << 26) /* Link Data Tx Error */ #define EDMA_IE_TRANSPROTERR (1 << 31) /* Transport Proto E */ #define EDMA_IE_TRANSIENT (EDMA_IE_LINKCTLRXERR(0x0b) | \ - EDMA_IE_LINKCTLTXERR(0x1f)) /* Non-fatal Errors */ + EDMA_IE_LINKCTLTXERR(0x1f)) + /* Non-fatal Errors */ #define EDMA_REQQBAH 0x10 /* Request Queue Base Address High */ #define EDMA_REQQIP 0x14 /* Request Queue In-Pointer */ #define EDMA_REQQOP 0x18 /* Request Queue Out-Pointer */ @@ -248,57 +250,63 @@ /* Serial-ATA Registers */ #define SATA_SS 0x300 /* SStatus */ -#define ATA_SS_DET_MASK 0x0000000f -#define ATA_SS_DET_NO_DEVICE 0x00000000 -#define ATA_SS_DET_DEV_PRESENT 0x00000001 -#define ATA_SS_DET_PHY_ONLINE 0x00000003 -#define ATA_SS_DET_PHY_OFFLINE 0x00000004 +#define SATA_SS_DET_MASK 0x0000000f +#define SATA_SS_DET_NO_DEVICE 0x00000000 +#define SATA_SS_DET_DEV_PRESENT 0x00000001 +#define SATA_SS_DET_PHY_ONLINE 0x00000003 +#define SATA_SS_DET_PHY_OFFLINE 0x00000004 -#define ATA_SS_SPD_MASK 0x000000f0 -#define ATA_SS_SPD_NO_SPEED 0x00000000 -#define ATA_SS_SPD_GEN1 0x00000010 -#define ATA_SS_SPD_GEN2 0x00000020 -#define ATA_SS_SPD_GEN3 0x00000040 +#define SATA_SS_SPD_MASK 0x000000f0 +#define SATA_SS_SPD_NO_SPEED 0x00000000 +#define SATA_SS_SPD_GEN1 0x00000010 +#define SATA_SS_SPD_GEN2 0x00000020 +#define SATA_SS_SPD_GEN3 0x00000040 -#define ATA_SS_IPM_MASK 0x00000f00 -#define ATA_SS_IPM_NO_DEVICE 0x00000000 -#define ATA_SS_IPM_ACTIVE 0x00000100 -#define ATA_SS_IPM_PARTIAL 0x00000200 -#define ATA_SS_IPM_SLUMBER 0x00000600 +#define SATA_SS_IPM_MASK 0x00000f00 +#define SATA_SS_IPM_NO_DEVICE 0x00000000 +#define SATA_SS_IPM_ACTIVE 0x00000100 +#define SATA_SS_IPM_PARTIAL 0x00000200 +#define SATA_SS_IPM_SLUMBER 0x00000600 #define SATA_SE 0x304 /* SError */ #define SATA_SEIM 0x340 /* SError Interrupt Mask */ -#define ATA_SE_DATA_CORRECTED 0x00000001 -#define ATA_SE_COMM_CORRECTED 0x00000002 -#define ATA_SE_DATA_ERR 0x00000100 -#define ATA_SE_COMM_ERR 0x00000200 -#define ATA_SE_PROT_ERR 0x00000400 -#define ATA_SE_HOST_ERR 0x00000800 -#define ATA_SE_PHY_CHANGED 0x00010000 -#define ATA_SE_PHY_IERROR 0x00020000 -#define ATA_SE_COMM_WAKE 0x00040000 -#define ATA_SE_DECODE_ERR 0x00080000 -#define ATA_SE_PARITY_ERR 0x00100000 -#define ATA_SE_CRC_ERR 0x00200000 -#define ATA_SE_HANDSHAKE_ERR 0x00400000 -#define ATA_SE_LINKSEQ_ERR 0x00800000 -#define ATA_SE_TRANSPORT_ERR 0x01000000 -#define ATA_SE_UNKNOWN_FIS 0x02000000 +#define SATA_SE_DATA_CORRECTED 0x00000001 +#define SATA_SE_COMM_CORRECTED 0x00000002 +#define SATA_SE_DATA_ERR 0x00000100 +#define SATA_SE_COMM_ERR 0x00000200 +#define SATA_SE_PROT_ERR 0x00000400 +#define SATA_SE_HOST_ERR 0x00000800 +#define SATA_SE_PHY_CHANGED 0x00010000 +#define SATA_SE_PHY_IERROR 0x00020000 +#define SATA_SE_COMM_WAKE 0x00040000 +#define SATA_SE_DECODE_ERR 0x00080000 +#define SATA_SE_PARITY_ERR 0x00100000 +#define SATA_SE_CRC_ERR 0x00200000 +#define SATA_SE_HANDSHAKE_ERR 0x00400000 +#define SATA_SE_LINKSEQ_ERR 0x00800000 +#define SATA_SE_TRANSPORT_ERR 0x01000000 +#define SATA_SE_UNKNOWN_FIS 0x02000000 #define SATA_SC 0x308 /* SControl */ -#define ATA_SC_DET_MASK 0x0000000f -#define ATA_SC_DET_IDLE 0x00000000 -#define ATA_SC_DET_RESET 0x00000001 -#define ATA_SC_DET_DISABLE 0x00000004 +#define SATA_SC_DET_MASK 0x0000000f +#define SATA_SC_DET_IDLE 0x00000000 +#define SATA_SC_DET_RESET 0x00000001 +#define SATA_SC_DET_DISABLE 0x00000004 + +#define SATA_SC_SPD_MASK 0x000000f0 +#define SATA_SC_SPD_NO_SPEED 0x00000000 +#define SATA_SC_SPD_SPEED_GEN1 0x00000010 +#define SATA_SC_SPD_SPEED_GEN2 0x00000020 +#define SATA_SC_SPD_SPEED_GEN3 0x00000040 -#define ATA_SC_SPD_MASK 0x000000f0 -#define ATA_SC_SPD_NO_SPEED 0x00000000 -#define ATA_SC_SPD_SPEED_GEN1 0x00000010 -#define ATA_SC_SPD_SPEED_GEN2 0x00000020 -#define ATA_SC_SPD_SPEED_GEN3 0x00000040 +#define SATA_SC_IPM_MASK 0x00000f00 +#define SATA_SC_IPM_NONE 0x00000000 +#define SATA_SC_IPM_DIS_PARTIAL 0x00000100 +#define SATA_SC_IPM_DIS_SLUMBER 0x00000200 -#define ATA_SC_IPM_MASK 0x00000f00 -#define ATA_SC_IPM_NONE 0x00000000 -#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 -#define ATA_SC_IPM_DIS_SLUMBER 0x00000200 +#define SATA_SC_SPM_MASK 0x0000f000 +#define SATA_SC_SPM_NONE 0x00000000 +#define SATA_SC_SPM_PARTIAL 0x00001000 +#define SATA_SC_SPM_SLUMBER 0x00002000 +#define SATA_SC_SPM_ACTIVE 0x00004000 #define SATA_LTM 0x30c /* LTMode */ #define SATA_PHYM3 0x310 /* PHY Mode 3 */ #define SATA_PHYM4 0x314 /* PHY Mode 4 */ @@ -374,11 +382,6 @@ #define MVS_MAX_PORTS 8 #define MVS_MAX_SLOTS 32 -/* Just to be sure, if building as module. */ -#if MAXPHYS < 512 * 1024 -#undef MAXPHYS -#define MAXPHYS 512 * 1024 -#endif /* Pessimistic prognosis on number of required S/G entries */ #define MVS_SG_ENTRIES (btoc(MAXPHYS) + 1) ==== //depot/projects/scottl-camlock/src/sys/dev/mvs/mvs_if.m#2 (text+ko) ==== @@ -22,7 +22,7 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# $FreeBSD: src/sys/dev/ata/ata_if.m,v 1.10 2010/01/20 14:29:55 rpaulo Exp $ +# $FreeBSD$ INTERFACE mvs; ==== //depot/projects/scottl-camlock/src/sys/dev/mvs/mvs_pci.c#5 (text+ko) ==== @@ -25,7 +25,7 @@ */ #include <sys/cdefs.h> -__FBSDID("$FreeBSD: src/sys/dev/mvs/mvs.c,v 1.30 2010/03/21 18:18:58 mav Exp $"); +__FBSDID("$FreeBSD$"); #include <sys/param.h> #include <sys/module.h> @@ -256,6 +256,7 @@ if (ctlr->ccc == 0) return; + /* CCC is not working for non-EDMA mode. Unmask device interrupts. */ mtx_lock(&ctlr->mtx); if (mode == MVS_EDMA_OFF) ctlr->pmim |= bit; @@ -338,12 +339,14 @@ ic = ATA_INL(ctlr->r_mem, CHIP_MIC); //device_printf(ctlr->dev, "irq MIC:%08x\n", ic); if (ctlr->msi) { + /* We have to to mask MSI during processing. */ mtx_lock(&ctlr->mtx); ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0); - ctlr->msia = 1; + ctlr->msia = 1; /* Deny MIM update during processing. */ mtx_unlock(&ctlr->mtx); } else if (ic == 0) return; + /* Acknowledge all-ports CCC interrupt. */ if (ic & IC_ALL_PORTS_COAL_DONE) ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS); for (p = 0; p < ctlr->channels; p++) { @@ -355,6 +358,7 @@ ic >>= 8; continue; } + /* Acknowledge interrupts of this HC. */ aic = 0; if (ic & (IC_DONE_IRQ << 0)) aic |= HC_IC_DONE(0) | HC_IC_DEV(0); @@ -368,6 +372,7 @@ aic |= HC_IC_COAL; ATA_OUTL(ctlr->r_mem, HC_BASE(p == 4) + HC_IC, ~aic); } + /* Call per-port interrupt handler. */ arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ); if ((arg.cause != 0) && (function = ctlr->interrupt[p].function)) { @@ -377,8 +382,9 @@ ic >>= 2; } if (ctlr->msi) { + /* Unmasking MSI triggers next interrupt, if needed. */ mtx_lock(&ctlr->mtx); - ctlr->msia = 0; + ctlr->msia = 0; /* Allow MIM update. */ ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim); mtx_unlock(&ctlr->mtx); } ==== //depot/projects/scottl-camlock/src/sys/dev/mvs/mvs_soc.c#5 (text+ko) ==== @@ -25,7 +25,7 @@ */ #include <sys/cdefs.h> -__FBSDID("$FreeBSD: src/sys/dev/mvs/mvs.c,v 1.30 2010/03/21 18:18:58 mav Exp $"); +__FBSDID("$FreeBSD$"); #include <sys/param.h> #include <sys/module.h> @@ -228,6 +228,7 @@ if (ctlr->ccc == 0) return; + /* CCC is not working for non-EDMA mode. Unmask device interrupts. */ mtx_lock(&ctlr->mtx); if (mode == MVS_EDMA_OFF) ctlr->pmim |= bit; @@ -295,6 +296,7 @@ //device_printf(ctlr->dev, "irq MIC:%08x\n", ic); if ((ic & IC_HC0) == 0) return; + /* Acknowledge interrupts of this HC. */ aic = 0; if (ic & (IC_DONE_IRQ << 0)) aic |= HC_IC_DONE(0) | HC_IC_DEV(0); @@ -307,6 +309,7 @@ if (ic & IC_HC0_COAL_DONE) aic |= HC_IC_COAL; ATA_OUTL(ctlr->r_mem, HC_IC, ~aic); + /* Call per-port interrupt handler. */ for (p = 0; p < ctlr->channels; p++) { arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ); if ((arg.cause != 0) &&
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