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Date:      Thu, 02 Mar 2006 15:25:16 -0700
From:      Scott Long <scottl@samsco.org>
To:        "M. Warner Losh" <imp@bsdimp.com>
Cc:        cvs-src@FreeBSD.org, gurney_j@resnet.uoregon.edu, src-committers@FreeBSD.org, ru@FreeBSD.org, cvs-all@FreeBSD.org
Subject:   Re: cvs commit: src/share/man/man9 bus_dma.9
Message-ID:  <440770CC.50001@samsco.org>
In-Reply-To: <20060302.141520.53336566.imp@bsdimp.com>
References:  <20060302071849.GH29183@ip.net.ua>	<20060302181629.GS840@funkthat.com>	<20060302185507.GM29183@ip.net.ua> <20060302.141520.53336566.imp@bsdimp.com>

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M. Warner Losh wrote:
> Here's what I came up with earlier in the week.
> 
> Index: bus_dma.9
> ===================================================================
> RCS file: /home/ncvs/src/share/man/man9/bus_dma.9,v
> retrieving revision 1.31
> diff -u -r1.31 bus_dma.9
> --- bus_dma.9	13 Dec 2005 17:07:52 -0000	1.31
> +++ bus_dma.9	2 Mar 2006 21:14:40 -0000
> @@ -265,14 +265,41 @@
>  .It Dv BUS_DMASYNC_PREREAD
>  Perform any synchronization required prior to an update of host memory by the
>  DMA read operation.
> +.Pp
> +In other words, the driver is about to command the device to start
> +a DMA operation that transfers data from the
> +device to the memory described by this map.
> +And pending writes to this part of memory that the CPU might have queued
> +up will either be discarded or be completed after this operation completes.
>  .It Dv BUS_DMASYNC_PREWRITE
>  Perform any synchronization required after an update of host memory by the CPU
>  and prior to DMA write operations.
> +.Pp
> +In other words, the CPU flushes any cached writes to the area of memory
> +described by this map so they are visible when the device does its
> +DMA READ operation on the memory described by the map.
> +An implementation may also use this to implement bounce buffers and
> +memory barriers.
>  .It Dv BUS_DMASYNC_POSTREAD
>  Perform any synchronization required after DMA read operations and prior to
>  CPU access to host memory.
> +.Pp
> +In other words, the CPU discards the cached values for the memory range
> +described by the map.
> +Future reads to the memory range described by the map will fetch the values
> +from memory.
> +An implementation is free to reload the cache before any driver initiated
> +reads to this memory.
> +An implementation may also use this to implement bounce buffers and
> +memory barriers.
>  .It Dv BUS_DMASYNC_POSTWRITE
>  Perform any synchronization required after DMA write operations.
> +.Pp
> +In other words, this is completely useless.
> +The driver writer has noticed that the device has indicated the DMA READ
> +operation has completed.
> +It is theoretically possible that this would cause the device to do something
> +but it is unclear what.
>  .El
>  .It Vt bus_dma_lock_t
>  Client specified lock/mutex manipulation method.

Pretty much factually correct, but not the kind of thing that I would 
commit to a man page.

Scott




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