Date: Sat, 8 Nov 2003 15:42:54 -0800 (PST) From: Juli Mallett <jmallett@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 41772 for review Message-ID: <200311082342.hA8Ngsw6018164@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=41772 Change 41772 by jmallett@jmallett_dalek on 2003/11/08 15:42:41 Add mips_barrier(), 8 NOPs and a memory barrier, to avoid any CP0/... hazards, and keep the compiler from doing *bad* things. Gets us much further. Oh how much pain has been caused by not working with the compiler. Affected files ... .. //depot/projects/mips/sys/mips/include/cpufunc.h#15 edit Differences ... ==== //depot/projects/mips/sys/mips/include/cpufunc.h#15 (text+ko) ==== @@ -34,33 +34,54 @@ #include <machine/cpuregs.h> static __inline void +mips_barrier(void) +{ + __asm __volatile (".set noreorder\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + ".set reorder\n\t" + : : : "memory"); +} + +static __inline void mips_tlbp(void) { __asm __volatile ("tlbp"); + mips_barrier(); } static __inline void mips_tlbr(void) { __asm __volatile ("tlbr"); + mips_barrier(); } static __inline void mips_tlbwi(void) { __asm __volatile ("tlbwi"); + mips_barrier(); } static __inline void mips_tlbwr(void) { __asm __volatile ("tlbwr"); + mips_barrier(); } static __inline void mips_wbflush(void) { __asm __volatile ("sync" : : : "memory"); + mips_barrier(); } #define MIPS_RDRW64_COP0(n,r) \ @@ -70,6 +91,7 @@ int v0; \ __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)";" \ : [v0] "=&r"(v0)); \ + mips_barrier(); \ return (v0); \ } \ static __inline void \ @@ -81,6 +103,7 @@ "nop;" \ : \ : [a0] "r"(a0)); \ + mips_barrier(); \ } MIPS_RDRW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0) @@ -98,6 +121,7 @@ int v0; \ __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)";" \ : [v0] "=&r"(v0)); \ + mips_barrier(); \ return (v0); \ } \ static __inline void \ @@ -109,6 +133,7 @@ "nop;" \ : \ : [a0] "r"(a0)); \ + mips_barrier(); \ } MIPS_RDRW32_COP0(compare, MIPS_COP_0_COMPARE)
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